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sprs009c january 1987 revised july 1991 tms320c1x digital signal processors post office box 1443 ? houston, texas 77001 copyright ? 1991, texas instruments incorporated 1 production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. ? performance up to 8.77 mips ? all tms320c1x devices are object code compatible ? 144/256-word on-chip data ram ? 1.5k/4k/8k-word on-chip program rom ? 4k-word on-chip program eprom (tms320e14/p14/e15/p15/e17/p17) ? one-time programmable (otp) versions available (tms320p14/p15/p17) ? eprom code protection for copyright security ? 4k / 64k-word total external memory at full speed ? 32-bit alu/accumulator ? 16 16-bit multiplier with a 32-bit product ? 0 to 16-bit barrel shifter ? eight input/output channels ? dual-channel serial port ? simple memory and i/o interface ? 5-v and 3.3-v versions available (tms320lc15/lc17) ? commercial and military versions available ? operating free-air temperature . . . 0 c to 70 c ? packaging: dip, plcc, quad flatpack, and cer-quad ? cmos technology: device cycle time e tms320c10 200-ns . . . . . . . . . . . . . . . . . . . e tms320c10-14 280-ns . . . . . . . . . . . . . . . . e tms320c10-25 160-ns . . . . . . . . . . . . . . . . e tms320c14 160-ns . . . . . . . . . . . . . . . . . . . e tms320e14 160-ns . . . . . . . . . . . . . . . . . . . e tms320p14 160-ns . . . . . . . . . . . . . . . . . . . e tms320c15 200-ns . . . . . . . . . . . . . . . . . . . e TMS320C15-25 160-ns . . . . . . . . . . . . . . . . e tms320e15 200-ns . . . . . . . . . . . . . . . . . . . e tms320e15-25 160-ns . . . . . . . . . . . . . . . . e tms320lc15 250-ns . . . . . . . . . . . . . . . . . . e tms320p15 200-ns . . . . . . . . . . . . . . . . . . . e tms320c16 114-ns . . . . . . . . . . . . . . . . . . . e tms320c17 200-ns . . . . . . . . . . . . . . . . . . . e tms320e17 200-ns . . . . . . . . . . . . . . . . . . . e tms320lc17 278-ns . . . . . . . . . . . . . . . . . . e tms320p17 200-ns . . . . . . . . . . . . . . . . . . . introduction the tms32010 digital signal processor (dsp), introduced in 1983, was the first dsp in the tms320 family. from it has evolved this tms320c1x generation of 16-bit dsps. all c1x dsps are object code compatible with the tms32010 dsp. the c1x dsps combine the flexibility of a high-speed controller with the numerical capability of an array processor, thereby offering an inexpensive alternative to multichip bit-slice processors. the highly paralleled architecture and efficient instruction set provide speed and flexibility to produce a cmos microprocessor generation capable of executing up to 8.77 mips (million instructions per second) ( c16). these c1x devices utilize a modified harvard architecture to optimize speed and flexibility, implementing functions in hardware that other processors implement through microcode or software. the c1x generation's powerful instruction set, inherent flexibility, high-speed number-handling capabilities, reduced power consumption, and innovative architecture have made these cost-effective dsps the ideal solution for many telecommunications, computer, commercial, industrial, and military applications. this data sheet provides detailed design documentation for the c1x dsps. it facilitates the selection of devices best suited for various user applications by providing specifications and special features for each c1x dsp. this data sheet is arranged as follows: introduction, quick reference table of device parameters and packages, summary overview of each device, architecture overview, and the c1x device instruction set summary. these are followed by data sheets for each c1x device providing available package styles, terminal function tables, block diagrams, and electrical and timing parameters. an index is provided to facilitate data sheet usage.
device sprs009c january 1987 revised july 1991 tms320c1x digital signal processors post office box 1443 ? houston, texas 77001 2 table 1 provides an overview of c1x processors with comparisons of memory, i/o, cycle timing, military support, and package types. for specific availability, contact the nearest ti field sales office. table 1. tms320c1x device overview memory i/o cycle package (1) ram rom eprom prog. serial parallel (ns) dip plcc cer-quad tms320c10 (2) 144 1.5k e 4k e 8 16 200 40 44 e tms320c10-14 144 1.5k e 4k e 8 16 280 40 44 e tms320c10-25 144 1.5k e 4k e 8 16 160 40 44 e tms320c14 (3) 256 4k e 4k 1 7 16 (4) 160 e 68 e tms320e14 (3) 256 e 4k 4k 1 7 16 (4) 160 e e 68 cer tms320p14 2 256 e 4k 4k 1 7 16 (4) 160 e 68 e tms320c15 (3) 256 4k e 4k e 8 16 200 40 44 e TMS320C15-25 256 4k e 4k e 8 16 160 40 44 e tms320e15 (3) 256 e 4k 4k e 8 16 200 40 e 44 cer tms320e15-25 256 e 4k 4k e 8 16 160 40 e 44 cer tms320lc15 256 4k e 4k e 8 16 250 40 44 e tms320p15 2 256 e 4k 4k e 8 16 200 40 44 e tms320c16 256 8k e 64k e 8 16 114 e e 64 qfp tms320c17 256 4k e e 2 6 16 (5) 200 40 44 e tms320e17 (5) 256 e 4k e 2 6 16 (5) 200 40 e 44 cer tms320lc17 (5) 256 4k e e 2 6 16 (5) 278 40 44 e tms320p17 (5) 2 256 e 4k e 2 6 16 (5) 200 40 44 2 one-time programmable (otp) device is in a windowless plastic package and cannot be erased. notes: 1. dip = dual in-line package. plcc = plastic-leaded chip carrier. cer = ceramic-leaded chip carrier. qfp = plastic quad f lat pack. 2. military version available. 3. military versions planned; contact nearest ti field sales office for availability. 4. on-chip 16-bit i/o, four capture inputs, and six compare outputs are available. 5. on-chip 16-bit coprocessor interface is optional by pin selection.
sprs009c january 1987 revised july 1991 tms320c1x digital signal processors post office box 1443 ? houston, texas 77001 3 description tms320c10 the c10 provides the core cpu used in all other c1x devices. its microprocessor operates at 5 mips. it provides a parallel i/o of 8 16 bits. three versions with cycle times of 160, 200, and 280 ns are available as illustrated in table 1. the c10 versions are offered in plastic 40-pin dip or a 44-lead plcc packages. tms320c14/e14/p14 the c14/e14/p14 devices, using the c10 core cpu, offer expanded on-chip ram, and rom or eprom ( e14/p14), 16 pins of bit selectable parallel i/o, an i/o mapped asynchronous serial port, four 16-bit timers, and external/internal interrupts. the c14 devices can provide for microcomputer/microprocessor operating modes. three versions with cycle times of 160-ns are available as illustrated in table 1. these devices are offered in 68-pin plastic plcc or ceramic cer-quad packages. tms320c15/e15/p15 the c15/e15/p15 devices are a version of the c10, offering expanded on-chip ram, and rom or eprom ( e15/p15). the p15 is a one-time programmable (otp), windowless eprom version. these devices can operate in the microcomputer or microprocessor modes. five versions are available with cycle times of 160 to 200 ns (see table 1). these devices are offered in 40-pin dip, 44-pin plcc, or 44-pin ceramic packages. tms320lc15 the lc15 is a low-power version of the c15, utilizing a v dd of only 3.3-v. this feature results in a 2.3: 1 power requirement reduction over the typical 5-v c1x device. it operates at a cycle time of 250 ns. the device is offered in 40-pin dip or 44-lead plcc packages. tms320c16 the c16 offers on-chip ram of 256-words, an expanded program memory of 64k-words, and a fast instruction cycle time of 114 ns (8.77 mips). it is offered in a 64-pin quad flat-pack package. tms320c17/e17/p17 the c17/e17/p17 versions consist of five major functional units: the c15 microcomputer, a system control register, a full-duplex dual channel serial port, m -law/a-law companding hardware, and a coprocessor port. the dual-channel serial port is capable of full-duplex serial communication and offers direct interface to two combo-codecs. the hardware companding logic can operate in either m -law or a-law format with either sign-magnitude or twos complement numbers in either serial or parallel modes. the coprocessor port allows the c17/e17/p17 to act as a slave microcomputer or as a master to a peripheral microcomputer. the p17 utilizes a one-time programmable (otp) windowless eprom version of the e17. tms320lc17 the lc17 is a low-power version of the c17, utilizing a v dd of only 3.3-v. this feature results in a 2.3: 1 power requirement reduction over the typical 5-v c1x device. it operates at a cycle time of 278 ns.
sprs009c january 1987 revised july 1991 tms320c1x digital signal processors post office box 1443 ? houston, texas 77001 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a1/pa1 a0/pa0 mc/mp rs int clkout x1 x2/clkin bio v ss d8 d9 d10 d11 d12 d13 d14 d15 d7 d6 a2/pa2 a3 a4 a5 a6 a7 a8 men den we v cc a9 a10 a11 d0 d1 d2 d3 d4 d5 tms320c10/c15/lc15/p15 n/jd packages (top view) tms320c10/c15/e15/lc15/p15 fn/fz packages (top view) clkout x1 x2/clkin bio nc v ss d8 d9 d10 d11 d12 a7 a8 men den we v cc a9 a10 a11 d0 d1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 int rs mc/mp a0/pa0 a1/pa1 a2/pa2 a3 a4 a5 a6 d13 d14 d15 d7 d6 d5 d4 d3 d2 cc v cc v v cc nc nc a0/pa0 a1/pa1 a2/pa2 a3 a4 a5 a6 v ss a7 a8 a9 a10 a11 a12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 a13 a14 nc nc rs x1 x2/clkin v ss v ss v ss v ss clkout d15 d14 nc d13 d12 d11 d10 d9 nc nc 20212223242526272829303132 64636261605958575655545352 d8 d7 d6 d5 d4 d3 d2 nc d1 d0 a15 nc bio int mc/mp v v v men nc ioen mwe iowe v dd dd dd dd v dd v ss tms320c16 pg package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pa1/rble pa0/hi/lo mc rs exint clkout x1 x2/clkin bio v ss d8/ld8 d9/ld9 d10/ld10 d11/ld11 d12/ld12 d13/ld13 d14/ld14 d15/ld15 d7/ld7 d6/ld6 pa2/tblf fsr fsx fr dx1 dx0 sclk dr1 den /rd we /wr v cc dr0 xf mc/pm d0/ld0 d1/ld1 d2/ld2 d3/ld3 d4/ld4 d5/ld5 tms320c17/e17/lc17/p17 n/jd packages (top view) d4 d5 d6 d7 iop0 iop1 iop2 iop3 iop4 iop5 d8 a9 cmp0 cmp1 a10 a11 cmp2 amp4/cap2/fsr d0 d1 d9 rxd/data txd/clk d10 iop6 iop7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9876543216867666564636261 tclk/clkr tclk2/clkx a8 a7 a6 we ren rs int clkout a5 a4 nmi /mc/mp wdt clkin a3 a2 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 a0 iop15 iop14 iop13 iop12 d14 iop11 iop10 d13 d12 iop9 iop8 d11 a1 d15 d3 d2 tms320c14/e14/p14 fn/fz packages (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 exint rs mc pao/hi/lo pa1/rble pa2/tblf fsr fsx fr dx1 d13/ld13 d14/ld14 d15/ld15 d7/ld7 d6/ld6 d5/ld5 d4/ld4 d3/ld3 d2/ld2 ss v d1/ld1 v ss clkout x1 x2/clkin bio nc v ss d8 d9 d10 d11 d12 dx0 sclk dr1 den /rd we /wr v cc dr0 xf mc/pm d0/ld0 v ss tms320c17/e17 fn/fz packages (top view) v cc1 v ss1 v cc2 v ss2 cmp3 cap0 cap1 cmp5/cap3/fsx
sprs009c january 1987 revised july 1991 tms320c1x digital signal processors post office box 1443 ? houston, texas 77001 5 architecture the c1x dsps use a modified harvard architecture for speed and flexibility. in a strict harvard architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch and one-cycle execution. the c1x dsps modification allows transfers between program and data spaces, thereby increasing the flexibility of the device. this modification permits coefficients stored in program memory to be read into the ram, eliminating the need for a separate coefficient rom. 32-bit accumulator all c1x devices contain a 32-bit alu and accumulator for support of double-precision, twos-complement arithmetic. the alu is a general-purpose arithmetic unit that operates on 16-bit words taken from the data ram or derived from immediate instructions. in addition to the usual arithmetic instructions, the alu can perform boolean operations, providing the bit manipulation ability required of a high-speed controller. the accumulator stores the output from the alu and is often an input to the alu. it operates with a 32-bit word length. the accumulator is divided into a high-order word (bits 31 through 16) and a low-order word (bits 15 through 0). instructions are provided for storing the high- and low-order accumulator words in memory. shifters two shifters are available for manipulating data. the alu barrel shifter performs a left-shift of 0 to 16 places on data memory words loaded into the alu. this shifter extends the high-order bit of the data word and zero-fills the low-order bits for twos-complement arithmetic. the accumulator parallel shifter performs a left-shift of 0, 1 or 4 places on the entire accumulator and places the resulting high-order accumulator bits into data ram. both shifters are useful for scaling and bit extraction. 16 16-bit parallel multiplier the multiplier performs a 16 16-bit twos-complement multiplication with a 32-bit result in a single instruction cycle. the multiplier consists of three units: the t register, p register, and a multiplier array. the 16-bit t register stores the multiplicand, and the p register stores the 32-bit product. multiplier values either come from the data memory or are derived immediately from the mpyk (multiply immediate) instruction word. the fast on-chip multiplier allows the device to perform fundamental operations such as convolution, correlation, and filtering. data and program memory since the c1x devices use a harvard type architecture, data and program memory reside in two separate spaces. these dsp devices have 144-or 256-words of on-chip data ram and 1.5k- to 8k-words of on-chip program rom. on-chip program eprom of 4k-words is provided in the e14/e15/e17 devices. an on-chip one-time programmable 4k-word eprom is provided in the p14/p15/p17 devices. the eprom cell utilizes standard prom programmers and is programmed identically to a 64k cmos eprom (tms27c64). (reference table 1.) program memory expansion all c1x devices except the c17/e17/lc17/p17 devices are capable of executing from off-chip external memory at full speed for those applications requiring external program memory space. this allows for external ram-based systems to provide multiple functionality. the c17/e17/lc17/p17 devices provide no external memory expansion. (reference table 1.) microcomputer/microprocessor operating modes all devices except the x17 offer two modes of operation defined by the state of the mc/mp pin: the microcomputer mode (mc/mp = 1) or the microprocessor mode (mc/mp = 0 ). in the microcomputer mode, on-chip rom is mapped into the program memory space. in the microprocessor mode, all words of progam memory are external.
sprs009c january 1987 revised july 1991 tms320c1x digital signal processors post office box 1443 ? houston, texas 77001 6 interrupts and subroutines all devices except the c16 contain a four-level stack for saving the contents of the program counter during interrupts and subroutine calls. because of the larger 64k program space, the c16's hardware stack has been increased to eight levels. instructions are available for saving the device's complete context. push and pop instructions permit a level of nesting restricted only by the amount of available ram. the interrupts used in these devices are maskable. input/output the 16-bit parallel data bus can be utilized to perform i/o functions in two cycles. the i/o ports are addressed by the three lsbs on the address lines. in addition, a polling input for bit test and jump operations (bio ) and an interrupt pin (int ) have been incorporated for multitasking. the bit selectable i/o of the c14 is suitable for microcontroller applications. serial port (tms320c17/e17) two of the i/o ports on the c17/e17 are dedicated to the serial port and companding hardware. i/o port 0 is dedicated to control register 0, which controls the serial port, interrupts, and companding hardware. i/o port 1 accesses control register 1, as well as both serial port channels, and companding hardware. the six remaining i/o ports are available for external parallel interfaces. serial port (tms320c14/e14) the c14/e14 devices include one i/o-mapped serial port that operates asynchronously. i/o-mapped control registers are used to configure port parameters such as inter-processor communication protocols and baud rate. companding hardware (tms320c17/e17) on-chip hardware enables the c17/e17 to compand (compress/expand) data in either m -law or a-law format. the companding logic operation is configured via the system control register. data may be companded in either serial mode for operation on serial port data (converting between linear and logarithmic pcm) or a parallel mode for computation inside the device. the c17/e17 allows the hardware companding logic to operate with either sign-magnitude or twos-complement numbers. coprocessor port (tms320c17/e17) the coprocessor port on the c17/e17 provides a direct connection to most microcomputers and microprocessors. the port is accessed through i/o port 5 using in and out instructions. the coprocessor interface allows the device to act as a peripheral (slave) microcomputer to a microprocessor, or as a master to a peripheral microcomputer. in the microcomputer mode, the 16 data lines are used for the 6 parallel 16-bit i/o ports. in the coprocessor mode, the 16-bit parallel port is reconfigured to operate as a 16-bit latched bus interface. for peripheral transfer, an 8-bit or 16-bit length of the coprocessor port can be selected.
sprs009c january 1987 revised july 1991 tms320c1x digital signal processors post office box 1443 ? houston, texas 77001 7 instruction set a comprehensive instruction set supports both numeric-intensive operations, such as signal processing, and general-purpose operations, such as high-speed control. all of the c1x devices are object-code compatible and use the same 60 instructions. the instruction set consists primarily of single-cycle single-word instructions, permitting execution rates of more than six million instructions per second. only infrequently used branch and i/o instructions are multicycle. instructions that shift data as part of an arithmetic operation execute in a single cycle and are useful for scaling data in parallel with other operations. note the bio pin on other c1x devices is not available for use in the c14/e14/p14. an attempt to execute the bioz (branch on bio low) instruction will result in a two cycle nop action. three main addressing modes are available with the instruction set: direct, indirect, and immediate addressing. direct addressing in direct addressing, seven bits of the instruction word concatenated with the 1-bit data page pointer form the data memory address. this implements a paging scheme in which the first page contains 128 words, and the second page contains up to 128 words. indirect addressing indirect addressing forms the data memory address from the least-significant eight bits of one of the two auxiliary registers, ar0-ar1. the auxiliary register pointer (arp) selects the current auxiliary register. the auxiliary registers can be automatically incremented or decremented and the arp changed in parallel with the execution of any indirect instruction to permit single-cycle manipulation of data tables. indirect addressing can be used with all instructions requiring data operands, except for the immediate operand instructions. immediate addressing immediate instructions derive data from part of the instruction word rather than from the data ram. some useful immediate instructions are multiply immediate (mpyk), load accumulator immediate (lack), and load auxiliary register immediate (lark). instruction set summary table 2 lists the symbols and abbreviations used in table 3, the instruction set summary. table 3 contains a short description and the opcode for each c1x instruction. the summary is arranged according to function and alphabetized within each functional group. table 2. instruction symbols symbol meaning acc accumulator d data memory address field m addressing mode bit k immediate operand field pa 3-bit port address field r 1-bit operand field specifying auxiliary register s 4-bit left-shift code x 3-bit accumulator left-shift field
d d k d d d d d d d d d d d k d d d s s x s no. cycles no. cycles no. words no. words d d d sprs009c january 1987 revised july 1991 tms320c1x digital signal processors post office box 1443 ? houston, texas 77001 8 table 3. tms320c1x instruction set summary accumulator instructions opcode mnemonic description instruction register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 abs absolute value of accumulator 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 add add to accumulator with shift 1 1 0 000 m addh add to high-order accumulator bits 1 1 0 1100000m adds add to accumulator with no sign extension 1 1 0 1100001m and and with accumulator 1 1 0 1111001m lac load accumulator with shift 1 1 0 010 m lack load accumulator immediate 1 1 0 1111110 or or with accumulator 1 1 0 1111010m sach store high-order accumulator bits with shift 1 1 0 1011 m sacl store low-order accumulator bits 1 1 0 1010000m sub subtract from accumulator with shift 1 1 0 001 m subc conditional subtract (for divide) 1 1 0 1100100m subh subtract from high-order accumulator bits 1 1 0 1100010m subs subtract from accumulator with no sign extension 1 1 0 1100011m xor exclusive or with accumulator 1 1 0 1111000m zac zero accumulator 1 1 0 1111111100 01001 zalh zero accumulator and load high-order bits 1 1 0 1100101m zals zero accumulator and load low-order bits with no sign extension 1 1 0 1100110m auxiliary register and data page pointer instructions opcode mnemonic description instruction register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lar load auxiliary register 1 1 0 0 1 1 1 0 0 r m lark load auxiliary register immediate 1 1 0 111000r larp load auxiliary register pointer immediate 1 1 0 1101000100 0000k ldp load data memory page pointer 1 1 0 1101111m ldpk load data memory page pointer immediate 1 1 0 1101110000 0000k mar modify auxiliary register and pointer 1 1 0 1101000m sar store auxiliary register 1 1 0 0 1 1 0 0 0 r m
branch address d branch address branch address branch address branch address branch address branch address branch address branch address branch address branch address d d d k b branch unconditionally 2 2 banz branch on auxiliary register not zero 2 2 bgez branch if accumulator 022 bgz branch if accumulator > 0 2 2 bioz branch on bio = 0 2 22 blez branch if accumulator 0 2 2 blz branch if accumulator < 0 2 2 bnz branch if accumulator 022 bv branch on overflow 2 2 bz branch if accumulator = 0 2 2 cala call subroutine from accumulator call call subroutine immediately 2 2 ret return from subroutine or interrupt routine no. cycles no. cycles no. words no. words sprs009c january 1987 revised july 1991 tms320c1x digital signal processors post office box 1443 ? houston, texas 77001 9 table 3. tms320c1x instruction set summary (continued) branch instructions opcode mnemonic description instruction register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 000 1 1110100000 00000 0 000 1 1111101000 00000 0 000 1 1111100000 00000 0 000 1 1110110000 00000 0 000 1 1111011000 00000 0 000 1 1111010000 00000 0 000 1 1111110000 00000 0 000 1 1110101000 00000 0 000 1 1111111000 00000 0 000 2 1 0 1111111100 01100 1 1111000000 00000 0 000 2 1 0 1111111100 01101 t register, p register, and multiply instructions opcode mnemonic description instruction register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 apac add p register to accumulator 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 lt load t register 1 1 0 1101010m lta lta combines lt and apac into one instruction 1 1 0 1101100m ltd ltd combines lt, apac, and dmov into one instruction 1 1 0 1101011m mpy multiply with t register, store product in p register 1 1 0 1101101m mpyk multiply t register with immediate operand; store product in p register 1 1 1 00 pac load accumulator from p register 1 1 0 1111111100 01110 spac subtract p register from accumulator 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 2 this instruction is a nop on the 320c14/e14/p14.
d d d d d pa d pa d no. cycles no. words no. cycles no. words sprs009c january 1987 revised july 1991 tms320c1x digital signal processors post office box 1443 ? houston, texas 77001 10 table 3. tms320c1x instruction set summary (concluded) control instructions opcode mnemonic description instruction register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dint disable interrupt 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 eint enable interrupt 1 1 0 1111111100 00010 lst load status register 1 1 0 1111011m nop no operation 1 1 0 1111111100 00000 pop pop stack to accumulator 2 1 0 1111111100 11101 push push stack from accumulator 2 1 0 1111111100 11100 rovm reset overflow mode 1 1 0 1111111100 01010 sovm set overflow mode 1 1 0 1111111100 01011 sst store status register 1 1 0 1111100m i/o and data memory operations opcode mnemonic description instruction register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dmov copy contents of data memory location into next higher location 1 1 0 1 1 0 1 0 0 1 m in input data from port 2 1 0 1000 m out output data to port 2 1 0 1001 m tblr table read from program memory to data ram 3 1 0 1100111m tblw table write from data ram to program memory 3 1 0 1 1 1 1 1 0 1 m
data (16) address (12) 144-word ram 1.5k-word rom 32-bit alu/acc multiplier shifters interrupt 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a1/pa1 a0/pa0 mc/mp rs int clkout x1 x2/clkin bio v ss d8 d9 d10 d11 d12 d13 d14 d15 d7 d6 a2/pa2 a3 a4 a5 a6 a7 a8 men den we v cc a9 a10 a11 d0 d1 d2 d3 d4 d5 tms320c10 n/jd package clkout x1 x2/clkin bio nc v ss d8 d9 d10 d11 d12 a7 a8 men den we v cc a9 a10 a11 d0 d1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 int rs mc/mp a0/pa0 a1/pa1 a2/pa2 a3 a4 a5 a6 d13 d14 d15 d7 d6 d5 d4 d3 d2 tms320c10 fn/fz package cc v ss v cc v +5 v gnd (top view) (top view) sprs009c january 1987 revised july 1991 tms320c10, tms320c10-14, tms320c10-25 digital signal processors post office box 1443 ? houston, texas 77001 11 key features: tms320c10 ? instruction cycle timing e 160-ns (tms320c10-25) e 200-ns (tms32010) e 280-ns (tms320c10-14) ? 144 words of on-chip data ram ? 1.5k words on-chip program rom ? external memory expansion up to 4k words at full speed ? 16 16-bit multiplier with 32-bit product ? 0 to 16-bit barrel shifter ? on-chip clock oscillator ? device packaging: e 40-pin dip e 44-lead plcc ? single 5-v supply ? operating free-air temperature range ...0 c to 70 c
sprs009c january 1987 revised july 1991 tms320c10, tms320c10-14, tms320c10-25 digital signal processors post office box 1443 ? houston, texas 77001 12 terminal functions name i/o 2 definition a11-a0/pa2-pa0 bio clkout d15-d0 den int mc/mp men nc rs v cc v ss we x1 x2/clkin o i o i/o o i i o o i i i o o i external address bus. i/o port address multiplexed over pa2-pa0. external polling input system clock output, 1/4 crystal/clkin frequency 16-bit parallel data bus data enable for device input data on d15-d0 external interrupt input memory mode select pin. high selects microcomputer mode. low selects microprocessor mode. memory enable indicates that d15-d0 will accept external memory instruction. no connection reset for initializing the device + 5 v supply ground write enable for device output data on d15-d0 crystal output for internal oscillator crystal input internal oscillator or external system clock input 2 input/output/high-impedance state.
sprs009c january 1987 revised july 1991 tms320c10, tms320c10-14, tms320c10-25 digital signal processors post office box 1443 ? houston, texas 77001 13 functional block diagram 3 12 d15-d0 32 16 16 16 32 shifter (0,1,4) 32 acc (32) 32 alu (32) data ram (144 words) address data 32 32 mux 32 16 p(32) t(16) multiplier shifter (016) 16 8 dp 7 mux 8 8 ar1 (16) ar0 (16) arp 16 16 data bus 16 16 16 program bus a11-a0/ pa2-pa0 12 instruction program rom/eprom (1.5k words) 3 rs int mc/mp bio men den we stack 4 12 12 12 pc (12) 12 12 lsb mux 16 x2/clkin clkout x1 controller mux mux address legend: acc = accumulator alu = arithmetic logic unit arp = auxiliary register pointer ar0 = auxiliary register 0 ar1 = auxiliary register 1 dp = data page pointer p = p register pc = program counter t = t register program bus data bus
v ih high-level input voltage v il low-level input voltage t a operating free-air temperature sprs009c january 1987 revised july 1991 tms320c10, tms320c10-14, tms320c10-25 digital signal processors post office box 1443 ? houston, texas 77001 14 electrical specifications this section contains the electrical specifications for all speed versions of the c10 digital signal processors, including test parameter measurement information. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range v cc (see note 6) 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous power dissipation 0.5 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature: l suffix 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a suffix 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating condit ionso section of this specification is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliabi lity. note 6: all voltage values are with respect to v ss. recommended operating conditions min nom max unit v cc supply voltage 4.5 5 5.25 v v ss supply voltage 0 v clkin 3 v all remaining inputs 2 v mc/mp 0.6 v all remaining inputs 0.8 v i oh high-level output current, all outputs 300 m a i ol low-level output current 2 ma l suffix 0 70 c a suffix 40 85 c
v m a m a pf pf v oh high-level output voltage i oz off-state output current c i input capacitance i i input current c o output capacitance f = 1 mhz, all other pins 0 v v cc = v ss to v cc v cc = max sprs009c january 1987 revised july 1991 tms320c10, tms320c10-14, tms320c10-25 digital signal processors post office box 1443 ? houston, texas 77001 15 electrical characteristics over specified temperature range (unless otherwise noted) parameter test conditions min typ 2 max unit i oh = max 2.4 3 i oh = 20 m a (see note 7) v cc 0.4 3 v ol low-level output voltage i ol = max 0.3 0.5 v v o = 2.4 v 20 v o = 0.4 v 20 all inputs except clkin 20 clkin 50 data bus 25 3 all others 15 3 data bus 25 3 all others 10 3 2 all typical values are at v cc = 5 v, t a = 25 c. 3 values derived from characterization data and not tested. note 7: this voltage specification is included for interface to hc logic. however, note that all of the other timing parameters defined in this data sheet are specified for ttl logic levels and will differ for hc logic levels. internal clock option c1 c2 crystal x1 x2/clkin figure 1. internal clock option parameter measurement information 2.15 v from output under test r l = 825 w test point c l = 100 pf figure 2. test load circuit
i cc 3 supply current ma crystal frequency, f x mhz r l = 825 w , c l = 100 pf (see figure 2) parameter unit test conditions unit sprs009c january 1987 revised july 1991 tms320c10, tms320c10-25 digital signal processors post office box 1443 ? houston, texas 77001 16 electrical characteristics over specified temperature range (unless otherwise noted) parameter test conditions (see figure 2) min typ 2 max unit tms320c10 f = 20.5 mhz, v cc = 5.5 v, t a = 40 c to 85 c 33 55 tms320c10-25 f = 25.6 mhz, v cc = 5.5 v t a = 0 c to 70 c 40 65 2 all typical values are at t a = 70 c and are used for thermal resistance calculations. 3 i cc characteristics are inversely proportional to temperature. for i cc dependence on temperature, frequency, and loading. clock characteristics and timing the c10/c10-25 can use either its internal oscillator or an external frequency source for a clock. internal clock option the internal oscillator is enabled by connecting a crystal across x1 and x2/clkin (see figure 1). the frequency of clkout is one-fourth the crystal fundamental frequency. the crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mw, and should be specified at a load capacitance of 20 pf. parameter test conditions min nom max unit tms320c10 t a = 40 c to 85 c 6.7 20.5 tms320c10-25 t a = 0 c to 70 c 6.7 25.6 c1, c2 t a = 40 c to 85 c 10 pf external clock option an external frequency source can be used by injecting the frequency directly into x2/clkin with x1 left unconnected. the external frequency injected must conform to the specifications listed in the table below. switching characteristics over recommended operating conditions tms320c10 tms320c10-25 min nom max min nom max t c(c) clkout cycle time 195.12 200 156.25 160 ns t r(c) clkout rise time 10 ? 10 ? ns t f(c) clkout fall time 8 ? 8 ? ns t w(cl) pulse duration, clkout low 92 ? 72 ? ns t w(ch) pulse duration, clkout high 90 ? 70 ? ns t d(mcc) delay time, clkin to clkout 25 ? 60 ? 25 50 ? ns t c(c) is the cycle time of clkout, i.e., 4t c(mc) (4 times clkin cycle time if an external oscillator is used). ? values derived from characterization data and not tested. timing requirements over recommended operating conditions tms320c10 tms320c10-25 min nom max min nom max t c(mc) master clock cycle time 48.78 50 150 39.06 40 150 ? ns t r(mc) rise time, master clock input 5 ? 10 ? 5 ? 10 ? ns t f(mc) fall time, master clock input 5 ? 10 ? 5 ? 10 ? ns t w(mcp) pulse duration, master clock 0.4t c(mc) ? 0.6t c(mc) ? 0.45t c(mc) ? 0.55t c(mc) ? ns t w(mcl) pulse duration, master clock low 20 ? 15 ? ns t w(mch) pulse duration, master clock high 20 ? 15 ? ns ? values derived from characterization data and not tested.
parameter test conditions unit r l = 825 w c l = 100 pf, (see figure 2) sprs009c january 1987 revised july 1991 tms320c10, tms320c10-25 digital signal processors post office box 1443 ? houston, texas 77001 17 memory and peripheral interface timing switching characteristics over recommended operating conditions tms320c10 tms320c10-25 min typ max min typ max t d1 delay time, clkout to address bus valid 10 2 50 10 2 40 ns t d2 delay time, clkout to men 1/4t c(c) 5 2 1/4t c(c) +15 1/4t c(c) 5 2 1/4t c(c) + 12 ns t d3 delay time, clkout to men 10 2 15 10 2 12 ns t d4 delay time, clkout to den 1/4t c(c) 5 21 / 4 t c(c) +15 1/4t c(c) 5 2 1/4t c(c) + 12 ns t d5 delay time, clkout to den 10 2 15 10 2 12 ns t d6 delay time, clkout to we 1/2t c(c) 5 2 1/2t c(c) + 15 1/2t c(c) 5 2 1/2t c(c) + 12 ns t d7 delay time, clkout to we 10 2 15 10 2 12 ns t d8 delay time, clkout to data bus out valid 1/4t c(c) + 65 1/4t c(c) + 52 2 ns t d9 time after clkout that data bus starts to be driven 1/4t c(c) 5 2 1/4t c(c) 5 2 ns t d10 time after clkout that data bus stops being driven 1/4t c(c) + 40 2 1/4t c(c) + 40 2 ns t v data bus out valid after clkout 1/4t c(c) 10 1/4t c(c) 10 ns t h(a-wmd) address hold time after we , men , or den (see note 8) 10 2 10 2 ns t su(a-md) address bus setup time prior to men or den 1/4t c(c) 45 1/4t c(c) 35 ns 2 values derived from characterization data and not tested. note 8: for interfacing i/o devices, see figure 3.
test condition r l = 825 w , c l = 100 pf (see figure 2) unit sprs009c january 1987 revised july 1991 tms320c10, tms320c10-25 digital signal processors post office box 1443 ? houston, texas 77001 18 timing requirements over recommended operating conditions tms320c10 tms320c10-25 min nom max min nom max t su(d) setup time, data bus valid prior to clkout 50 40 ns t h(d) hold time, data bus held valid after clkout (see note 9) 0 0 ns note 9: data may be removed from the data bus upon men or den preceding clkout . suggested i/o decode circuit the circuit shown in figure 3 is a design example for interfacing i/o devices to the c10/c10-25. this circuit decodes the address for output operations using the out instruction. the same circuit can be used to decode input and output operations if the inverter ('als04) is replaced with a nand gate and both den and we are connected. inputs and outputs can be decoded at the same port provided the output of the decoder ('as137) is gated with the appropriate signal (den or we ) to select read or write (using an 'als32). access times can be increased when the circuit shown in figure 3 is repeated to support in instructions with den connected rather than we . the table write (tblw) function requires a different circuit. a detailed discussion of an example circuit for this function is described in the application report, ainterfacing external memory to the tms32010o, published in the book, digital signal processing applications with the tms320 famil y (spra012a). tms320c10 74as137 gl a b c g1 g 2 4 1 2 3 6 5 2 1 40 pa0 pa1 pa2 74als04 32 y0 y1 y2 y3 y4 y5 y6 y7 15 14 13 12 11 10 9 7 i/o device v cc we figure 3. i/o decode circuit
unit unit parameter unit r l 825 w , c l = 100 pf, (see figure 2) sprs009c january 1987 revised july 1991 tms320c10, tms320c10-25 digital signal processors post office box 1443 ? houston, texas 77001 19 reset (rs ) timing switching characteristics over recommended operating conditions parameter test conditions min typ max unit t d11 delay time, den , we , and men from rs 1/2t c(c) +502 ns t dis(r) data bus disable time after rs 1/4t c(c) +50 2 ns 2 values derived from characterization data and not tested. timing requirements over recommended operating conditions tms320c10 tms320c10-25 min nom max min nom max t su(r) reset (rs ) setup time prior to clkout (see note 10) 50 40 ns t w(r) rs pulse duration 5t c(c) 5t c(c) ns note 10: rs can occur anytime during a clock cycle. time given is minimum to ensure synchronous operation. interrupt (int ) timing timing requirements over recommended operating conditions tms320c10 tms320c10-25 min nom max min nom max t f(int) fall time, int 15 15 ns t w(int) pulse duration, int t c(c) t c(c) ns t su(int) setup time, int before clkout 50 40 ns io (bio ) timing timing requirements over recommended operating conditions tms320c10 tms320c10-25 min nom max min nom max t f(io) fall time, bio 15 15 ns t w(io) pulse duration, bio t c(c) t c(c) ns t su(io) setup time, bio before clkout 50 40 ns
r l = 825 w , c l = 100 pf, (see figure 2) tms320c10-14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 20 electrical characteristics over specified temperature range (unless otherwise noted) parameter test conditions min typ 2 max unit i cc 3 supply current f = 14.4, mhz, v cc = 5.5 v, t a = 0 c to 70 c 28 65 ma 2 all typical values are at t a = 70 c and are used for thermal resistance calculations. 3 i cc characteristics are inversely proportional to temperature; i.e., i cc decreases approximately linearly with temperature. clock characteristics and timing the tms320c10-14 can use either its internal oscillator or an external frequency source for a clock. internal clock option the internal oscillator is enabled by connecting a crystal across x1 and x2/clkin (see figure 1). the frequency of clkout is one-fourth the crystal fundamental frequency. the crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mw, and be specified at a load capacitance of 20 pf. parameter test conditions min nom max unit crystal frequency, f x t a = 0 c to 70 c 6.7 14.4 mhz c1, c2 t a = 0 c to 70 c 10 pf external clock option an external frequency source can be used by injecting the frequency directly into x2/clkin with x1 left unconnected. the external frequency injected must conform to the specifications listed in the table below. switching characteristics over recommended operating conditions test conditions min nom max unit t c(c) clkout cycle time 277.78 ns t r(c) clkout rise time 10 ns t f(c) clkout fall time 8 ns t w(cl) pulse duration, clkout low 131 ns t w(ch) pulse duration, clkout high 129 ns t d(mcc) delay time, clkin to clkout 25 ? 60 ? ns t c(c) is the cycle time of clkout, i.e., 4t c(mc) (4 times clkin cycle time if an external oscillator is used). ? values derived from characterization data and not tested. timing requirements over recommended operating conditions min nom max unit t c(mc) master clock cycle time 69.5 150 ns t r(mc) rise time, master clock input 5 ? 10 ? ns t f(mc) fall time, master clock input 5 ? 10 ? ns t w(mcp) pulse duration, master clock 0.4t c(mc) ? 0.6t c(mc) ? ns t w(mcl) pulse duration, master clock low, t c(mc) = 50 ns 20 ? ns t w(mch) pulse duration, master clock high, t c(mc) = 50 ns 20 ? ns ? values derived from characterization data and not tested.
r l = 825 w , c l = 100 pf (see figure 2) r l = 825 w , c l = 100 pf (see figure 2) tms320c10-14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 21 memory and peripheral interface timing switching characteristics over recommended operating conditions parameter test conditions min nom max unit t d1 delay time, clkout to address bus valid 10 2 50 ns t d2 delay time, clkout to men 1/ 4 t c(c) 5 2 1/ 4 t c(c) +15 ns t d3 delay time, clkout to men 10 2 15 ns t d4 delay time, clkout to den 1/ 4 t c(c) 5 21 / 4 t c(c) +15 ns t d5 delay time, clkout to den 10 2 15 ns t d6 delay time, clkout to we 1/ 2 t c(c) 5 2 1/ 2 t c(c) +15 ns t d7 delay time, clkout to we 10 2 15 ns t d8 delay time, clkout to data bus out valid 1/4t c(c) + 65 ns t d9 time after clkout that data bus starts to be driven 1/4t c(c) 5 2 ns t d10 time after clkout that data bus stops being driven 1/4t c(c) + 40 2 ns t v data bus out valid after clkout 1/4t c(c) 10 ns t h(a-wmd) address hold time after we , men , or den (see note 8) 10 2 ns t su(a-md) address bus setup time prior to men or den 1/4t c(c) 45 ns 2 values derived from characterization data and not tested. note 8: for interfacing i/o devices, see figure 3. timing requirements over recommended operating conditions test conditions min nom max unit t su(d) setup time, data bus valid prior to clkout 50 ns t h(d) hold time, data bus held valid after clkout (see note 9) 0 ns note 9: data may be removed from the data bus upon men or den preceding clkout .
r l = 825 w , c l = 100 pf (see figure 2) tms320c10-14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 22 reset (rs ) timing switching characteristics over recommended operating conditions parameter test conditions min typ max unit t d11 delay time, den , we , and men from rs 1/2t c(c) + 50 2 ns t dis(r) data bus disable time after rs 1/4t c(c) + 50 2 ns 2 values were derived from characterization data and not tested. timing requirements over recommended operating conditions min nom max unit t su(r) reset (rs ) setup time prior to clkout (see note 10) 50 ns t w(r) rs pulse duration 5t c(c) ns note 10: rs can occur anytime during a clock cycle. time given is minimum to ensure synchronous operation. interrupt (int ) timing timing requirements over recommended operating conditions min nom max unit t f(int) fall time, int 15 ns t w(int) pulse duration, int t c(c) ns t su(int) setup time, int before clkout 50 ns io (bio ) timing timing requirements over recommended operating conditions min nom max unit t f(io) fall time, bio 15 ns t w(io) pulse duration, bio t c(c) ns t su(io) setup time, bio before clkout 50 ns
tms320c10, tms320c10-14, tms320c10-25 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 23 timing diagrams timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2 volts, unless otherwise noted. clock timing t r(mc) t c(mc) t w(mch) t w(mcp) 2 t f(mc) t w(mcl) t d(mcc) 2 t w(ch) t w(cl) t r(c) t c(c) t f(c) x2/clkin clkout 2 t d(mcc) and t w(mcp) are referenced to an intermediate level of 1.5 v on the clkin waveform. memory read timing t c(c) t d3 t d2 t d1 t h(a-wmd) t su(d) t h(d) address bus valid t su(a-md) instruction valid clkout men a11-a0 d15-d0
tms320c10, tms320c10-14, tms320c10-25 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 24 tblr instruction timing clkout men a11-a0 d15-d0 12 3 4 5678 t d2 t d3 t d3 t su(d) t h(d) t d1 9101112 legend: 1. tblr instruction prefetch 7. address bus valid 2. dummy prefetch 8. address bus valid 3. data fetch 9. instruction valid 4. next instruction prefetch 10. instruction valid 5. address bus valid 11. data input valid 6. address bus valid 12. instruction valid tblw instruction timing men a11-a0 we d15-d0 12 3 4567 891011 t d6 t d10 t d8 t d7 t d9 t v clkout legend: 1. tblw instruction prefetch 7. address bus valid 2. dummy prefetch 8. instruction valid 3. next instruction prefetch 9. instruction valid 4. address bus valid 10. data output valid 5. address bus valid 11. instruction valid 6. address bus valid
tms320c10, tms320c10-14, tms320c10-25 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 25 in instruction timing clkout men a11-a0 den d15-d0 t su(d) t h(d) t su(a-md) t d5 t d4 12 345 678 legend: 1. in instruction prefetch 5. address bus valid 2. next instruction prefetch 6. instruction valid 3. address bus valid 7. data input valid 4. peripheral address valid 8. instruction valid out instruction timing clkout men a11-a0 we d15-d0 12 34 5 678 t d6 t d7 t v t d9 t d10 t d8 legend: 1. out instruction prefetch 5. address bus valid 2. next instruction prefetch 6. instruction valid 3. address bus valid 7. data output valid 4. peripheral address valid 8. instruction valid
tms320c10, tms320c10-14, tms320c10-25 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 26 reset timing t su(r) t su(r) t w(r) t dis(r) t d11 clkout rs den we men d15-d0 men address bus (see note e) data shown relative to we data in from pc addr 0 data in from pc addr pc+1 ab = address bus ab = pc ab = pc+1 ab = pc = 0 ab = pc+1 data out notes: a. rs forces den , we , and men high and places data bus d0 through d15 in a high-impedance state. ab outputs (and program count- er) are synchronously cleared to zero after the next complete clk cycle from rs . b. rs must be maintained for a minimum of five clock cycles. c. resumption of normal program will commence after one complete clk cycle from rs . d. due to the synchronization action on rs , time to execute the function can vary dependent upon when rs or rs occur in the clk cycle. e. diagram shown is for definition purpose only. den , we , and men are mutually exclusive. f. during a write cycle, rs may produce an invalid write address. interrupt timing clkout t su(int) t w(int) t f(int) int bio timing clkout bio t su(io) t w(io) t f(io)
tms320c10, tms320c10-14, tms320c10-25 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 27 typical power vs. frequency graphs 1.2 4 8 12 16 20 24 28 10 16 22 28 34 40 46 52 v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v f x - crystal frequency - mhz (a) 40 c to 85 c temperature range 1.2 4 8 12 16 20 24 28 0 6 12 18 24 30 36 42 f x - crystal frequency - mhz (b) voltage = 5 v; temperature = 25 c without load with load t a = 40 c t a = 85 c t a = 40 c t a = 85 c t a = 40 c t a = 85 c i cc - supply current - ma i cc - supply current - ma figure 4. typical cmos i cc vs frequency
32-bit alu/acc multiplier shifters interrupt data (16) address (12) +5 v gnd 256-word ram 8k-word rom/ eprom d4 d5 d6 d7 iop0 iop1 iop2 iop3 iop4 iop5 d8 a9 cmp0 cmp1 a10 a11 cmp2 amp4/cap2/fsr d0 d1 d9 rxd/data txd/clk d10 iop6 iop7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9876543216867666564636261 tclk/clkr tclk2/clkx a8 a7 a6 we ren rs int clkout a5 a4 nmi /mc/mp wdt clkin a3 a2 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 a0 iop15 iop14 iop13 iop12 d14 iop11 iop10 d13 d12 iop9 iop8 d11 a1 d15 d3 d2 tms320c14, tms320e14/p14 fn/fz packages (top view) v cc1 v ss1 v cc2 v ss2 cmp3 cap0 cap1 cmp5/cap3/fsx tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 28 key features: tms320c14/e14/p14 ? 160-ns instruction cycle ? 256 words of on-chip data ram ? 4k words of on-chip program rom (tms320c14) ? 4k words of on-chip program eprom (tms320e14/p14) ? one-time programmable (otp) windowless eprom version available ( 320p14) ? eprom code protection for copyright security ? external memory expansion up to 4k-words at full speed (microprocessor mode) ? 16 16-bit multipler with 32-bit product ? 0 to 16-bit barrel shifter ? seven input and seven output external ports ? bit selectable i/o port (16 pins) ? 16-bit bidirectional data bus with greater than 50-mbps transfer rate ? asynchronous serial port ? 15 internal/external interrupts ? event manager with capture inputs and compare outputs ? four independent timers [watchdog, general purpose (2), serial port] ? four-level hardware stack ? packaging: 68-pin plcc (fn suffix) or clcc (fz suffix) ? single 5-v supply ? operating free-air temperature ...0 c to 70 c
tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 29 introduction the c14/e14/p14 are 16/32-bit single-chip digital signal processing (dsp) microcontrollers that combine the high performance of a dsp with on-chip peripherals. with a 160-ns instruction cycle, these devices are capable of executing up to 6.4 million instructions per second (mips). the c14/e14/p14 dsps are ideal for applications such as automotive control systems, computer peripherals, industrial controls, and military command/control system applications. control-specific on-chip peripherals include: an event manager with 6 channel pwm d/a/, 6-bit i/o pins, an asynchronous serial port, four 16-bit timers, and internal/external interrupts. with 4k-words of on-chip rom, the c14 is a mask programmable device. code is provided by the customer, and ti incorporates the customer's code into the photomask. it is offered in a 68-pin plastic chip carrier package (fn suffix), rated for operation from 0 c to 70 c. the e14 is provided with a 4k-word on-chip eprom. this eprom version is excellent for prototyping and for customized applications. it is programmable with standard eprom programmers. it is offered in a 68-pin (windowed) cerquad package (fz suffix), rated for operation from 0 c to 70 c. the p14 features a one-time programmable 4k-word on-chip eprom. the p14 is provided in an unprogrammed state and is programmed as if it were a blank e14. it is offered in a low-cost, volume-production-oriented, 68-pin plastic leaded chip carrier (plcc) package (fn suffix), rated for operation from 0 c to 70 c.
i/o/z 2 tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 30 each device can execute programs form either internal (mc/mp =0) or external program memory (mc/mp =1). for proprietary code security, the e14 and p14 incorporate an eprom protect bit (rbit). if this bit is programmed, the device's internal program memory cannot be accessed by any external means. terminal functions pin description name no. address/data buses a11 a10 a9 a8 a7 a6 a5 a4 a3 a2/pa2 a1/pa1 a0/pa0 5 6 9 12 13 14 20 21 25 26 27 28 o/z program memory address bus a11 (msb) through a0 (lsb) and port addresses pa2 (msb) through pa0 (lsb). addresses a11 through a0 are always active and never go to high impedance except during reset. during execution of the in and out instructions, pins 26, 27, and 28 carry the port addresses. pins a3 through a11 are held high when port accesses are made on pins pa0 through pa2. d15 msb d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lsb 35 36 39 40 43 46 49 50 57 58 59 60 61 62 63 64 i/o/z parallel data bus d15 (msb) through d0 (lsb). the data bus is always in the high-impedance state except when we is active (low). the data bus is also active when internal peripherals are written to. interrupt and miscellaneous signals int 18 i external interrupt input. the interrupt signal is generated by a high-to-low transition on this pin. nmi /mc/mp 22 i non-maskable interrupt. when this pin is brought low, the device is interrupted irrespective of the state of the intm bit in status register st. microcomputer/microprocessor select. this pin is also sampled when rs is low. if high during reset, internal program memory is selected. if low during reset, external memory will be selected. we 15 o write enable. when active low, we indicates that device will output data on the bus. ren 16 o read enable. when active low, ren indicates that device will accept data from the bus. rs 17 i reset. when this pin is low, the device is reset and pc is set to zero. continued next page. 2 input/output/high-impedance state.
i/o/z 2 tms320c10-14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 31 terminal functions (concluded) pin description name no. supply/oscillator signals clkout 19 o system clock output (one fourth clkin frequency). v cc 4,33 i 5-v supply pins. v ss 3,34 i ground pins. clkin 24 i master clock input from external clock source. serial port and timer signals rxd 48 i asynchronous mode receive input. txd 47 o/z asynchronous mode transmit output. tclk1 10 i timer 1 clock. if external clock is selected, it serves as clock input to timer 1. tclk2 11 i timer 2 clock. if external clock is selected, it serves as clock input to timer 2. wdt 23 o watchdog timer output. an active low is generated on this pin when the watchdog timer times out. bit i/o pins iop15 msb iop14 iop13 iop12 iop11 iop10 iop9 iop8 iop7 iop6 iop5 iop4 iop3 iop2 iop1 iop0 lsb 29 30 31 32 37 38 41 42 44 45 51 52 53 54 55 56 i/o 16 bit i/o lines that can be individually configured as inputs or outputs and also individually set or reset when configured as outputs. compare and capture signals cmp0 cmp1 cmp2 cmp3 8 7 2 1 o compare outputs. the states of these pins are determined by the combination of compare and action registers. cap0 cap1 68 67 i capture inputs. a transition on these pins causes the timer register to be captured in fifo stack. cmp4/cap2 66 i/o this pin can be configured as compare output or capture input. cmp5/cap3 65 i/o this pin can be configured as compare output or capture input. 2 input/output/high-impedance state.
tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 32 functional block diagram we ren rs iop0-iop15 rxd txd cap0,1 cmp4, 5 / cap2, 3 cmp0-cmp3 iop 9 9 serial port timer serial port controller cap detect (4) 4 16 4 16 fifo stack (4) 16 6 16 16 act (6) cmpr (6) 32 wdt d15-d0 tclk1.2 16 watchdog timer 12 12 32 16 16 16 32 shifter (0,1,4) 32 acc (32) 32 data (256 words) address data 32 32 16 p(32) t(16) multiplier shifter (016) 16 8 dp 7 8 8 ar1 (16) ar0 (16) arp 16 16 16 16 16 a0-a11 pa0-pa2 16 instruction program rom/eprom (4k words) 3 stack 4 12 12 12 pc (12) 12 12 lsb 16 clkout clkin program bus controller mux timers 1.2 mux address mux mux mux alu (32) legend: dp = data page pointer acc = accumulator iop = input/output port act = action register (bit selectable) alu = arithmetic logic unit pc = program counter arp = auxiliary register point p = p register ar0 = auxiliary register 0 rbr = receive buffer register ar1 = auxiliary register 1 rsr = receive shift register bsr = bank select register t = t register cap = capture tbr = transmit buffer register cmpr = compare register tsr = transmit shift register 1 tbr rbr tsr rsr 16 16 data bus 16 bsr 16 interrupt controller nmi / mc/mp int data bus 16 architecture the c1x family utilizes a modified harvard architecture for speed and flexibility. in a strict harvard architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch and execution. the c1x family's modification of a harvard architecture allows transfers between program and data spaces, thereby increasing the flexibility of the device. this modification permits coefficients stored in program memory to be read into the ram, eliminating the need for a separate coefficient rom. it also makes available immediate instructions and subroutines based on computed values. 32-bit alu/accumulator the c14/e14/p14 devices contain a 32-bit alu and accumulator for support of double-precision, twos-complement arithmetic. the alu is a general-purpose arithmetic unit that operates on 16-bit words taken from the data ram or derived from immediate instructions. in addition to the usual arithmetic instructions, the alu can perform boolean operations, providing the bit manipulation ability required of a high-speed controller.
tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 33 the accumulator stores the output from the alu and is often an input to the alu. it operates with a 32-bit wordlength. the accumulator is divided into a high-order word (bits 31 through 16) and a low-order word (bits 15 through 0). instructions are provided for storing the high- and low- order accumulator words in memory. shifters two shifters are available for manipulating data. the alu barrel shifter performs a left-shift of 0 to16 places on data memory words loaded into the alu. this shifter extends the high-order bit of the data word and zero-fills the low-order bits for twos-complement arithmetic. the accumulator parallel shifter performs a left-shift of 0, 1, or 4 places on the entire accumulator and places the resulting high-order accumulator bits into data ram. both shifters are useful for scaling and bit extraction 16 16-bit parallel multiplier the multiplier performs a 16 16-bit twos-complement multiplication with a 32-bit result in a single instruction cycle. the multiplier consists of three units: the t register, p register, and the multiplier array. the 16-bit t register temporarily stores the multiplicand; the p register stores the 32-bit product. multiplier values either come from the data memory or are derived immediately from the mpyk (multiply immediate) instruction word. the fast on-chip multiplier allows the device to perform fundamental operations such as convolution, correlation, and filtering. data and program memory since the c14/e14/p14 devices use a harvard architecture, data and program memory reside in two separate spaces. these devices have 256 words of on-chip data ram and 4k words of on-chip program rom ( c14) or eprom ( e14 and the otp p14). the eprom cell utilizes standard prom programmers and is programmed identically to a 64k-bit cmos eprom (tms27c64). program memory expansion the c1x devices are capable of executing up to 4k words of external memory at full speed for those applications requiring external program memory space. this allows for external ram-based systems to provide multiple functionality. microcomputer/microprocessor operating modes the c14/e14/p14 devices offer two modes of operation defined by the state of the nmi /mc/mp pin during reset: the microcomputer mode (nmi /mc/mp is high) or the microprocessor mode (nmi /mc/mp is low). in the microcomputer mode, the on-chip rom is mapped into the program memory space. in the microprocessor mode, all 4k words of memory are external. interrupts and subroutines the c14/e14/p14 devices contain a four-level hardware stack for saving the contents of the program counter during interrupts and subroutine calls. instructions are available for saving the complete context of the device. push and pop instructions permit a level of nesting restricted only by the amount of available ram. the c14/e14/p14 have a total of 15 internal/external interrupts. fourteen of these are maskable; nmi is the fifteenth. input/output the 16-bit parallel data bus can be utilized to access external peripherals. however, only the lower three address lines are active. the upper nine address lines are driven high. bit i/o the c14/e14/p14 has 16 pins of bit i/o that can be individually configured as inputs or outputs. each of the pins can be set or cleared without affecting the others. the input pins can also detect and match patterns and generate a maskable interrupt signal to the cpu. serial port the c14/e14/p14 includes an i/o-mapped asynchronous serial port.
tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 34 event manager an event manager is included that provides up to four capture inputs and up to six compare outputs. this peripheral operates with the timers to provide a form of programmable event logging/detection. the six compare outputs can also be configured to produce six channels of high precision pwm. timers 1 and 2 two identical 16-bit timers are provided for general purpose applications. both timers include a 16-bit period register and buffer latch, and can generate a maskable interrupt. serial port timer the serial port timer is a 16-bit timer primarily intended for baud rate generation for the serial port. its architecture is the same as timers 1 and 2, therefore it can serve as a general purpose timer if not needed for serial communication. watchdog timer the c14/e14/p14 contain a 16-bit watchdog timer that can produce a timeout (wdt ) signal for various applications such as software development and event monitoring. the watchdog timer also generates, at the point of the timeout, a maskable interrupt signal to the cpu. instruction set a comprehensive instruction set supports both numeric-intensive operations, such as signal processing, and general-purpose operations, such as high-speed control. all of the first-generation devices are object-code compatible and use the same 60 instructions. the instruction set consists primarily of single-cycle single-word instructions, permitting execution rates of more than six million instructions per second. only infrequently used branch and i/o instructions are multicycle. instructions that shift data as part of an arithmetic operation execute in a single cycle and are useful for scaling data in parallel with other operations. note the bio pin on other c1x devices is not available for use in the c14/e14/p14 devices. an attempt to execute the bioz (branch on bio low) instruction will result in a two cycle nop action. three main addressing modes are available with the instruction set: direct, indirect, and immediate addressing. direct addressing in direct addressing, seven bits of the instruction word concatenated with the 1-bit data page pointer from the data memory address. this implements a paging scheme in which each page contains 128 words. indirect addressing indirect addressing forms the data memory address from the least-significant eight bits of one of the two auxiliary registers, ar0 and ar1. the auxiliary register pointer (arp) selects the current auxiliary register. the auxiliary registers can be automatically incremented or decremented and the arp changed in parallel with the execution of any indirect instruction to permit single-cycle manipulation of data tables. indirect addressing can be used with all instructions requiring data operands, except for the immediate operand instructions. immediate addressing immediate instructions derive data from part of the instruction word rather than from part of the data ram. some useful immediate instructions are multiply immediate (mpyk), load accumulator immediate (lack), and load auxiliary register immediate (lark).
v ih high-level input voltage v v cc supply voltage tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 35 electrical specifications this section contains all the electrical specifications for the c14/e14/p14 devices, including test parameter measurement information. parameters with pp subscripts apply only to the e14 and p14 in the eprom programming mode. absolute maximum ratings over specified temperature range (unless otherwise noted) 2 supply voltage range, v cc (see note 6) 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range, v pp (see note 6) 0.6 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range 0.3 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous power dissipation 0.5 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . air temperature range above operating device: l version 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 55 c + 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating condit ionso section of this specification is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliabi lity. note 6: all voltage values are with respect to v ss . recommended operating conditions min nom max unit operating voltage 4.75 5 5.25 v fast programming 5.75 6 6.25 v snap! pulse programming 6.25 6.5 6.75 v v pp supply voltage for fast programming (see note 11) 12.25 12.5 12.75 v v pp supply voltage for snap! pulse programming (see note 11) 12.75 13 13.25 v v ss supply voltage 0 v clkin, cap0, cap1, cmp4/cap2, cmp5/cap3, rs 3 all remaining inputs 2 v il low-level input voltage, all inputs 0.8 v i oh high-level output current, all outputs 300 m a i ol low-level output current, all outputs 2 ma t a operating free-air temperature 0 70 c note 11: v pp can be applied only to programming pins designed to accept v pp as an input. during programming the total supply current is i pp + i cc .
v oh high-level output voltage i oz off-state output voltage i i input current v cc = max m a v i = v ss to v cc m a c i input capacitance pf c o output capacitance pf f = 1 mhz, all other pins 0 v tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 36 electrical characteristics over specified temperature range (unless otherwise noted) parameter test conditions min typ 2 max unit i oh = max 2.4 3 v i oh = 20 m a (see note 7) v cc 0.4 2 v v ol low-level output voltage i ol = max 0.3 0.5 v v o = 2.4 v 20 v o = 0.4 v 20 all other inputs except clkin 20 clkin 50 i cc supply current f = 25.6 mhz, v cc = 5.25 v, t a = 0 c to 70 c 70 90 ma i pp1 v pp supply current v pp = v cc = 5.5 v 100 m a i pp2 v pp supply current (during program pulse) v pp = 13 v 30 50 ma data bus 25 3 all others 15 3 data bus 25 3 all others 10 3 2 all typical values are at v cc = 5 v, t a = 25 c, except i cc at 70 c. 3 values derived from characterization data and not tested. i cc characteristics are inversely proportional to temperature. note 7: this voltage specification is included for interface to hc logic. however, note that all of the other timing parameters defined in this data sheet are specified for ttl logic levels and will differ for hc logic levels. parameter measurement information 2.15 v from output under test r l = 825 w test point c l = 100 pf figure 5. test load circuit external clock requirements the tms320c14/e14/p14 use an external frequency source for a clock. this source is applied to the clkin pin, and must conform to the specifications in the table below. parameters test conditions min nom max unit clkin input clock frequency t a = 0 c to 70 c 6.7 25.6 mhz
r l = 825 w , c l = 100 pf, (see figure 2) tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 37 clock timing switching characteristics over recommended operating conditions parameter test conditions min nom max unit t c(c) clkout cycle time 3 156.25 600 ns t r(c) clkout rise time 10 2 ns t f(c) clkout fall time 8 2 ns t w(cl) pulse duration, clkout low 72 2 ns t w(ch) pulse duration, clkout high 70 2 ns t d(mcc) delay time clkin to clkout 45 2 ns 2 values were derived from characterization data and not tested. timing requirements over recommended operating conditions min nom max unit t c(mc) master clock cycle time 3 39.06 40 150 ns t r(mc) rise time, master clock input 5 2 10 2 ns t f(mc) fall time, master clock input 5 2 10 2 ns t w(mcp) pulse duration, master clock 0.45 t c(mc) 2 0.55 t c(mc) 2 ns t w(mcl) pulse duration, master clock low 15 2 130 ns t w(mch) pulse duration, master clock high 15 2 130 ns 2 values were derived from characterization data and not tested. 3 t c(c) is the cycle time of clkout, i.e., 4t c(mc) (4 times clkin cycle time if an external oscillator is used).
r l = 825 w , c l = 100 pf, (see figure 2) r l = 825 w , c l = 100 pf, (see figure 2) r l = 825 w , c l = 100 pf, (see figure 2) r l = 825 w , c l = 100 pf, (see figure 2) tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 38 memory read and instruction timing switching characteristics over recommended operating conditions parameter test conditions min nom max unit t su(a)r address bus valid before ren 0.25 t c(c) 39 ns t su(a)w address bus valid before we 0.50 t c(c) 45 ns t h(a) address bus valid after ren or we 5 2 ns t en(d)w data starts being driven before we 0.25 t c(c) 2 ns t su(d)w data valid prior to we 0.25 t c(c) 45 ns t h(d)w data valid after we 0.25 t c(c) 10 ns t dis(d)w data in high impedance after we 0.25 t c(c) + 25 2 ns t w(wel) we -low duration 0.50 t c(c) 15 ns t w(renl) ren -low duration 0.75 t c(c) 15 ns t rec(we) write recovery time, time between we and ren 0.25 t c(c) 5 ns t rec(ren) read recovery time, time between ren and we 0.50 t c(c) 10 ns t d(we-clk) time from we to clkout 0.50 t c(c) 15 ns 2 values were derived from characterization data and not tested. timing requirements over recommended operating conditions test conditions min nom max unit t su(d)r data set-up prior to ren 52 ns t h(d)r data hold after ren 0 ns t a(a) access time for read cycle data valid after valid address t c(c) 90 ns t oe(ren) access time for read cycle from ren 0.75 t c(c) 60 ns t dis(d)r data in high impedance after ren 0.25 t c(c) 2 ns reset (rs ) timing switching characteristics over recommended operating conditions parameter test conditions min nom max unit t d(rs-rw) delay from rs to ren and we 0.75 t c(c) + 20 2 ns t dis(rs-rw) delay from rs to ren and we into high impedance 1.25 t c(c) 2 ns t dis(rs-db) data bus disable after rs 1.25 t c(c) 2 ns t dis(rs-ab) address bus disable after rs t c(c) 2 ns t en(rs-ab) address bus enable after rs t c(c) 2 ns timing requirements over recommended operating conditions test conditions min nom max unit t su(rs) rs setup prior to clkout (see note 10) 60 ns t w(rs) rs pulse duration 5t c(c) ns note 10: rs can occur anytime during the clock cycle. time given is minimum to ensure synchronous operation.
r l = 825 w , c l = 100 pf, (see figure 2) r l = 825 w , c l = 100 pf, (see figure 2) r l = 825 w , c l = 100 pf, (see figure 2) tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 39 microcomputer/microprocessor mode (nmi /mc/mp ) timing requirements over recommended operating conditions min nom max unit t h(mc/mp) 3 hold time after rs high t c(c) ns 2 values were derived from characterization data and not tested. 3 hold time to put device in microprocessor mode. interrupt (int )/nonmaskable interrupt (nmi ) timing requirements over recommended operating conditions min nom max unit t f(int) fall time, int 15 2 ns t f(nmi) fall time, nmi 15 2 ns t w(int) pulse duration, int t c(c) ns t w(nmi) pulse duration, nmi t c(c) ns t su(int) setup time, int before clkout low (see note 12) 60 ns t su(nmi) setup time, nmi before clkout low (see note 12) 60 ns note 12: int and nmi are synchronous inputs and can occur at any time during the cycle. nmi and int are edge triggered only. bit i/o timing switching characteristics over recommended operating conditions parameter test conditions min nom max unit t rfo(iop) rise and fall time outputs 20 2 ns t d(iop) clkout low to data valid outputs 0.75 t c(c) +80 ns timing requirements over recommended operating conditions test conditions min nom max unit t rfl(iop) rise and fall time inputs 20 2 ns t su(iop) data setup time before clkout time 40 ns t w(iop) input pulse duration t c(c) ns general purpose timers timing requirements over recommended operating conditions test conditions min nom max unit t r(tim) tclk1, tclk2 rise time 20 2 ns t f(tim) tclk1, tclk2 fall time 20 2 ns t wl(tim) tclk1, tclk2 low time t c(c) +20 ns t wh(tim) tclk1, tclk2 high time t c(c) +20 ns t clk(tim) input pulse duration 2 t c(c) +40 ns 2 values were derived from characterization data and not tested.
r l = 825 w , c l = 100 pf, (see figure 2) r l = 825 w , c l = 100 pf, (see figure 2) r l = 825 w , c l = 100 pf, (see figure 2) tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 40 watchdog timer timing switching characteristics over recommended operating conditions parameter test conditions min nom max unit t f(wdt) fall time, wdt 20 2 ns t d(wdt) clkout to wdt valid 0.25 t c(c )+20 ns t w(wdt) wdt output pulse duration 7 t c(c ) ns event manager timer switching characteristics over recommended operating conditions parameter test conditions min nom max unit t f(cmp) fall time, cmp0-cmp5 20 2 ns t r(cmp) rise time, cmp0-cmp5 20 2 ns timing requirements over recommended operating conditions test conditions min nom max unit t w(cap) cap0-cap3 input pulse duration t c(c) +20 ns t su(cap) capture input setup time before clkout low 20 2 ns 2 values were derived from characterization data and not tested.
tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 41 timing diagrams timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2 volts, unless otherwise noted. clock timing t r(mc) t c(mc) t w(mch) t w(mcp) 2 t f(mc) t w(mcl) t d(mcc) 2 t w(ch) t w(cl) t r(c) t c(c) t f(c) x2/clkin clkout 2 t d(mcc) and t w(mcp) are referenced to an intermediate level of 1.5 v on the clkin waveform. memory read timing t h(a) t su(d)r t h(d)r address bus valid t su(a)r instruction input valid ren a11-a0 d15-d0 t w(renl) t oe(ren) t a(a)
tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 42 tblr instruction timing ren a11-a0 d15-d0 12 3 4 5678 t su(d)r t h(d)r 910 1112 t su(a)r t a(a) legend: 1. tblr instruction prefetch 7. address bus valid 2. dummy prefetch 8. address bus valid 3. data fetch 9. instruction input valid 4. next instruction prefetch 10. instruction input valid 5. address bus valid 11. data input valid 6. address bus valid 12. instruction input valid tblw instruction timing ren a11-a0 we d15-d0 12 3 4567 891011 t en(d)w 2 t h(d)w t dis(d)w t su(d)w 2 t w(wel) 2 data valid prior to we legend: 1. tblw instruction prefetch 7. address bus valid 2. dummy prefetch 8. instruction input valid 3. next instruction prefetch 9. instruction input valid 4. address bus valid 10. data output valid 5. address bus valid 11. instruction input valid 6. address bus valid
tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 43 in instruction timing ren a11-a0 d15-d0 t su(d)r t h(d)r t su(a)r 12 456 789 t a(a) 3 legend: 1. in instruction prefetch 6. address bus valid 2. data fetch 7. instruction input valid 3. next instruction prefetch 8. data input valid 4. address bus valid 9. instruction input valid 5. peripheral address valid out instruction timing ren a11-a0 we d15-d0 1 45 67 t w(wel) 3 t dis(d)w t en(d)w t h(d)w t su(d)w 2 legend: 1. out instruction prefetch 5. address bus valid 2. next instruction prefetch 6. instruction input valid 3. address bus valid 7. data output valid 4. peripheral address valid
tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 44 reset timing t su(rs) t su(rs) t w(rs) t dis(rs-db) t d(rs-rw) clkout rs ren we d15-d0 address bus (see note e) data shown relative to we data in from pc addr 0 data in from pc addr pc+1 ab = address bus ab = pc ab = pc = 0 ab = pc+1 t dis(rs-rw) t dis(rs-ab) t en(rs-ab) data out notes: a. rs forces ren , and we high and then places data bus d0-d15, ren , we , and address bus a0-a11 in a high-impedance state. ab outputs (and program counter) are synchronously cleared to zero after the next complete clk cycle from rs . b. rs must be maintained for a minimum of five clock cycles. c. resumption of normal program will commence after one complete clk cycle from rs . d. due to the synchronization action on rs , time to execute the function can vary dependent upon when rs or rs occur in the clk cycle. e. diagram shown is for definition purpose only. we and ren are mutually exclusive. microcomputer/microprocessor mode timing clkout rs t h(mc/mp) nmi /mc/mp
tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 45 interrupt timing t su(int) , t su(nmi) nm i or int clkout t w(int) , t w(nmi) t f(int) , t f(nmi) bit i/o timing t w(iop) t rfi(iop) t rfo(iop) t su(iop) clkout iop15-iop0 (output) iop15-iop0 (input) general purpose timers t wl(tim) tclk1, tclk2 t f(tim) t r(tim) t wh(tim) t clk(tim) watchdog timer t f(wdt) t d(wdt) wdt clkout t w(wdt)
tms320c14, tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 46 event manager t w(cap) t su(cap) t f(cmp) / t r(cmp) clkout cap3-cap0 cmp5-cmp0
tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 47 programming the tms320e14/p14 eprom cell the e14 and p14 include a 4k 16-bit industry-standard eprom cell for prototyping and low-volume production. the c14 with a 4k-word masked rom then provides a migration path for cost-effective production. an eprom adapter socket (part # tmdx3270110), shown in figure 5, is available to provide 68-pin to 28-pin conversion for programming the e14 and p14. key features of the eprom cell include the normal programming operation as well as verification. the eprom cell also includes a code protection feature that allows code to be protected against copyright violations. the e14/p14 eprom cells are programmed using the same family and device codes as the tms27c64 8k 8-bit eprom. the tms27c64 eprom series are ultraviolet-light erasable, electrically programmable, read-only memories, fabricated using hvcmos technology. they are pin compatible with existing 28-pin roms and eproms. these eproms operate from a 5-v supply in the read mode; however, a 12.5-v supply is needed for programming. all programming signals are ttl level. for programming outside the system, existing eprom programmers can be used. locations may be programmed singly, in blocks, or at random. figure 5. eprom adapter socket the e14/p14 devices use 13 address lines to address the 4k-word memory in byte format (8k-byte memory). in word format, the most-significant byte of each word is assigned an even address and the least-significant byte an odd address in the byte format. programming information should be downloaded to eprom programmer memory in a high-byte to low-byte order for proper programming of the devices (see figure 6).
tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 48 1234h 5678h 9abch defoh . . . 0(0000h) 1(000ah) 2(0002h) 3(0003h) . . . 4095(0ffh) tms320c14 on-chip program memory (word format) 0(0000h) 1(0001h) 2(0002h) 3(0003h) 4(0004h) 5(0005h) 6(0006h) 7(0007h) . . . 0(0000h) 1(0001h) 2(0002h) 3(0003h) 4(0004h) 5(0005h) 6(0006h) 7(0007h) . . . 8191(1fffh) tms320e14 and tms320p14 on- chip program memory (byte format) eprom programmer memory byte format with adapter socket 34h 12h 78h 56h bch 9ah foh deh . . . 12h 34h 56h 78h 9ah bch deh foh . . . figure 6. programming data format figure 7 shows the wiring conversion to program the e14 and p14 using the 28-pin pinout of the tms27c64. the table of pin nomenclature provides a description of the tms27c64 pins. caution the e14 and p14 do not support the signature mode available with some eprom programmers. the signature mode places high voltage (12.5 v dc ) on pin a9. the e14 and p14 eprom cells are not designed for this feature and will be damaged if subjected to it. a 3.9 k w resistor is standard on the ti programmer socket between pin a9 and programmer. this protects the device from unintentional use of the signature mode. 3.9 k w a0 a1 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 clkin g e v pp ept pgm a12 a11 a10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 q4 q5 q6 q7 q8 e a10 g a11 a9 a8 ept pgm v cc gnd q3 q2 q1 a0 a1 a2 a3 a4 a5 a6 a7 a12 v pp tms27c64 pinout 14 13 12 11 10 9 8 7 6 5 4 3 2 1 tms320e14 tms320p14 a9 a8 v v a7 a6 a5 a4 a3 a2 cc ss q8 q7 q6 q5 cc ss q4 q3 q2 q1 v v figure 7. tms320e14/p14 eprom programming conversion to tms27c64 eprom pinout
tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 49 terminal functions (tms320e14/p14) name i/o definition a12(msb)-a0(lsb) clkin e ept g gnd pgm q8(msb)-q1(lsb) rs v cc v pp i i i i i i i i/o i i i on-chip eprom programming address lines clock oscillator input eprom chip enable eprom test mode select eprom output enable ground eprom write/program select data lines for byte-wide programming of on-chip 8k bytes of eprom reset for initializing the device 5-v to 6.5-v power supply 12.5-v to 13-v power supply table 4 shows the programming levels required for programming, verifying, reading, and protecting the eprom cell. table 4. tms320e14/p14 programming mode levels signal name 2 tms320e14/p14 pin tms27c64 pin program program verify read eprom protect protect verify e 19 20 v il v il v il v ih v il g 23 22 v ih pulse pulse v ih v il pgm 16 27 pulse v ih v ih v ih v ih v pp 18 1 v pp v pp v cc v pp v ccp v cc 4,33 28 v ccp v ccp v cc v ccp v ccp v ss 3,34 14 v ss v ss v ss v ss v ss clkin 24 14 v ss v ss v ss v ss v ss ept 17 26 v ss v ss v ss v pp v pp q1-q8 42, 41, 38, 37, 32-29 1113, 15-19, data in data out data out q 8 = pulse q 8 = rbit a12-a7 15, 11, 10, 8, 7, 2 2, 23, 21, 24, 25, 3 addr addr addr x x a6 1 4 addr addr addr x v il a5 68 5 addr addr addr x x a4 67 6 addr addr addr v ih x a3-a0 66, 65, 56, 55 7-10 addr addr addr x x 2 signal names shown for e14/p14 eprom programming mode only. legend: v ih = ttl high level; v il = ttl low level; addr = byte address bit; v pp = 12.5 v 0.25 v (fast) or 13 v 0.25 v (snap! pulse). v cc =5 v 0.25 v; x = don't care; pulse = low-going ttl pulse. d in = byte to be programmed at addr; q out = byte stored at addr.; rbit = rom protect bit v ccp =6 v 0.25 v (fast) or 6.5 v 0.25 v (snap! pulse). programming since every memory in the cell is at a logic high, the programming operation reprograms selected bits to low. once the 320e14 is programmed, these bits can only be erased using ultraviolet light. the correct byte is placed on the data bus with v pp set to the 12.5-v level. the pgm pin is then pulsed low to program in the zeros.
t w(pgm) initial program pulse duration tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 50 erasure before programming, the e14 must be erased by exposing it to ultraviolet light. the recommended minimum exposure dose (uv-intensity exposure-time) is 15 w ? s/cm 2 . a typical 12-mw ? s/cm 2 , filterless uv lamp will erase the device in 21 minutes. the lamp should be located about 2.5 cm above the chip during erasure. after exposure, all bits are in the high state. verify/read to verify correct programming, the eprom cell can be read using either the verify or read line definitions shown in table 5, assuming the inhibit bit (rbit) has not been programmed. program inhibit programming may be inhibited by maintaining a high level input on the e pin or pgm pin. standard programming procedure before programming, the e14 must first be completely erased. the device can then be programmed with the correct code. it is advisable to program unused sections with zeros as a further security measure. after the programming is complete, the code programmed into the cell should be verified. if the cell passes verification, the next step is to program the rom protect bit (rbit). once the rbit programming is verified, an opaque label should be placed over the window to protect the eprom cell from inadvertent erasure by ambient light. at this point, the programming is complete, and the device is ready to be placed into its destination circuit. refer to other appendices of the tms320c1x user's guide for additional information on eprom programming. recommended timing requirements for programming: v cc = 6 v and v pp = 12.5 v (fast) or v cc = 6.5 v and v pp = 13 v (snap! pulse), t a = 25 c (see note 13) min nom max unit fast programming algorithm 0.95 1 1.05 ms snap! pulse programming algorithm 95 100 105 m s t w(fpgm) final pulse duration fast programming only 2.85 78.75 ms t su(a) address setup time 2 m s t su(e) e setup time 2 m s t su(g) g setup time 2 m s t su(d) data setup time 2 m s t su(vpp) v pp setup time 2 m s t su(vcc) v cc setup time 2 m s t h(a) address hold time 0 m s t h(d) data hold time 2 m s note 13: for all switching characteristics and timing measurements, input pulse levels are 0.4 v to 2.4 v and v pp = 12.5 v 0.5 v during programming.
tms320e14, tms320p14 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 51 program cycle timing a12-a0 q8-q1 v pp v cc e pgm g program verify address n+1 v ih v il v ih /v oh v il /v ol v pp v cc v ccp v cc v ih v il v ih v il v ih v il hi-z data in stable address stable t su(a) data out valid t dis(g) 2 t h(a) t su(d) t su(vpp) t su(vcc) t su(e) t w(fpgm) t su(g) t en(g) 2 t h(d) 2 t dis(g) and t en(g ) are characteristics of the device but must be accommodated by the programmer.
data (16) address (12) 256-word ram 4k-word rom/eprom 32-bit alu/acc multiplier shifters interrupt 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a1/pa1 a0/pa0 mc/mp rs int clkout x1 x2/clkin bio v ss d8 d9 d10 d11 d12 d13 d14 d15 d7 d6 a2/pa2 a3 a4 a5 a6 a7 a8 men den we v cc a9 a10 a11 d0 d1 d2 d3 d4 d5 tms320c15/e15/lc15/p15 n/jd package (top view) clkout x1 x2/clkin bio nc v ss d8 d9 d10 d11 d12 a7 a8 men den we v cc a9 a10 a11 d0 d1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 int rs mc/mp a0/pa0 a1/pa1 a2/pa2 a3 a4 a5 a6 d13 d14 d15 d7 d6 d5 d4 d3 d2 tms320c15/e15/lc15/p15 fn/fz package (top view) cc v ss v cc v +5 v or +3.3 v gnd tms320c15, tms320e15, tms320lc15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 52 key features: tm320c15/e15/lc15/p15 ? instruction cycle timing: e 160-ns (TMS320C15-25/e15-25) e 200-ns (tms320c15/e15/p15) e 250-ns (tms320lc15) ? 256 words of on-chip data ram ? 4k words of on-chip program rom (tms320c15/c15-25/lc15) ? 4k words of on-chip program eprom (tms320e15/e15-25) ? one-time programmable (otp) windowless eprom version available (tms320p15) ? eprom code protection for copyright security ? external memory up to 4k-words at full speed ? 16 16-bit multiplier with 32-bit product ? 0 to 16-bit barrel shifter ? on-chip clock oscillator ? 3.3-v low-power version available (tms320lc15) ? device packaging: e 40-pin dip (all devices) e 44-lead plcc (tms320c15/c15-25/lc15/p15) e 44-lead-quad (tms320e15/e15-25)
tms320c15, tms320e15, tms320lc15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 53 functional block diagram 3 12 d15-d0 32 16 16 16 32 shifter (0,1,4) 32 acc (32) 32 alu (32) data ram (256 words) address data 32 32 mux 32 16 p(32) t(16) multiplier shifter (016) 16 8 dp 7 mux 8 8 ar1 (16) ar0 (16) arp 16 16 data bus 16 16 16 program bus a11-a0/ pa2-pa0 12 instruction program rom/eprom (4k words) 3 rs int mc/mp bio men den we stack 4 12 12 12 pc (12) 12 12 lsb mux 16 x2/clkin clkout x1 controller mux mux address legend: acc = accumulator alu = arithmetic logic unit arp = auxiliary register pointer ar0 = auxiliary register 0 ar1 = auxiliary register 1 dp = data page pointer p = p register pc = program counter t = t register program bus data bus
tms320c15, tms320e15, tms320lc15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 54 terminal functions (tms320c15/e15/lc15/p15) 2 name i/o 3 definition a11-a0/pa2-pa0 bio clkout d15-d0 den int mc/mp men nc rs v cc v ss we x1 x2/clkin o i o i/o o i i o o i i i o o i external address bus. i/o port address multiplexed over pa2-pa0. external polling input system clock output, 1/4 crystal/clkin frequency 16-bit parallel data bus data enable for device input data on d15-d0 external interrupt input memory mode select pin. high selects microcomputer mode. low selects microprocessor mode. memory enable indicates that d15-d0 will accept external memory instruction. no connection reset for initializing the device + 5 v supply ground write enable for device output data on d15-d0 crystal output for internal oscillator crystal input internal oscillator or external system clock input 2 see eprom programming section. 3 input/output/high-impedance state.
v ih high-level input voltage v il low-level input voltage t a operating free-air temperature v cc supply voltage tms320c15, tms320e15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 55 electrical specifications this section contains the electrical specifications for the c15/e15/p15 digital signal processors, including test parameter measurement information. parameters with pp subscripts apply only to the e15/p15 in the eprom programming mode (see note 11). absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v cc (see note 6) 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range, v pp 0.6 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range 0.3 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous power dissipation 0.5 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature: l suffix 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a suffix 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating condit ionso section of this specification is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliabi lity. note 6: all voltage values are with respect to v ss. recommended operating conditions min nom max unit eprom devices 4.75 5 5.25 v all other devices 4.5 5 5.5 v v pp supply voltage (see note 11) 12.25 12.5 12.75 v v ss supply voltage 0 v clkin 3 v all remaining inputs 2 v mc/mp 0.6 v all remaining inputs 0.8 v i oh high-level output current, all outputs 300 m a i ol low-level output current (all outputs except for tms320lc15) 2 ma l suffix 0 70 c a suffix 40 85 c note 11: v pp can be applied only to programming pins designed to accept v pp as an input. during programming the total supply current is i pp + i cc .
v oh high-level output voltage v cc = max v i = v ss to v cc i oz off-state output current i i input current i cc 3 supply current c i input capacitance c o output capacitance f = 1 mhz, all other pins 0 v pf pf ma m a m a crystal frequency, f x mhz tms320c15, tms320e15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 56 electrical characteristics over specified temperature range (unless otherwise noted) parameter test conditions min typ 2 max unit i oh = max 2.4 3 v i oh = 20 m a (see note 8) v cc 0.4 v v ol low-level output voltage i ol = max 0.3 0.5 v v o = 2.4 v 20 v o = 0.4 v 20 all inputs except clkin 20 clkin 50 tms320c15 f = 20.5 mhz, v cc = 5.5 v, t a = 0 c to 70 c 45 55 TMS320C15-25 f = 25.6 mhz, v cc = 5.5 v, t a = 0 c to 70 c 50 65 tms320e15 f = 20.5 mhz, v cc = 5.25 v, t a = 40 c to 85 c 55 75 tms320e15-25 f = 25.6 mhz, v cc = 5.25 v, t a = 0 c to 70 c 65 85 data bus 25 3 all other 15 3 data bus 25 3 all others 10 3 2 all typical values are at v cc = 5 v, t a = 70 c and are used for thermal resistance calculations. 3 i cc characteristics are inversely proportional to temperature. for i cc dependence on temperature, frequency, and loading, see figure 3. note 7: this voltage specification is included for interface to hc logic. however, note that all of the other timing parameters defined in this data sheet are specified for ttl logic levels and will differ for hc logic levels. clock characteristics and timing the tms320c15/e15/p15 can use either its internal oscillator or an external frequency source for a clock. internal clock option the internal oscillator is enabled by connecting a crystal across x1 and x2/clkin (see figure 1). the frequency of clkout is one-fourth the crystal fundamental frequency. the crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mw, and should be specified at a load capacitance of 20 pf. parameter test conditions min nom max unit tms320c15 t a = 0 c to 70 c 6.7 20.5 tms320e15/p15 t a = 40 c to 85 c 6.7 20.5 TMS320C15-25/e15-25 t a = 0 c to 70 c 6.7 25.6 c1, c2 t a = 0 c to 70 c 10 pf
unit parameter test conditions r l = 825 w , c l = 100 pf (see figure 2) tms320c15, tms320e15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 57 external clock option an external frequency source can be used by injecting the frequency directly into x2/clkin with x1 left unconnected. the external frequency injected must conform to the specifications listed in the table below. switching characteristics over recommended operating conditions tms320c15/e15/p15 TMS320C15-25/e15-25 min nom max min nom max t c(c) clkout cycle time 3 195.12 200 156.25 160 ns t r(c) clkout rise time 10 2 10 2 ns t f(c) clkout fall time 8 2 8 2 ns t w(cl) pulse duration, clkout low 92 2 72 2 ns t w(ch) pulse duration, clkout high 90 2 70 2 ns t d(mcc) delay time, clkin to clkout 25 2 60 2 25 2 50 2 ns 2 values derived from characterization data and not tested. 3 t c(c) is the cycle time of clkout, i.e., 4t c(mc) (4 times clkin cycle time if an external oscillator is used).
unit r l = 825 w , c l = 100 pf (see figure 2) test conditions parameter unit r l = 825 w , c l = 100 pf (see figure 2) unit test conditions tms320c15, tms320e15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 58 timing requirements over recommended operating conditions tms320c15/e15/p15 TMS320C15-25/e15-25 min nom max min nom max t c(mc) master clock cycle time 48.78 50 150 39.06 40 150 ns t r(mc) rise time, master clock input 5 2 10 2 5 2 10 2 ns t f(mc) fall time, master clock input 5 2 10 2 5 2 10 2 ns t w(mcp) 2 pulse duration, master clock 0.4t c(mc) 0.6t c(mc) 2 0.45t c(mc) 0.55t c(mc) 2 ns t w(mcl) pulse duration, master clock low 20 2 15 2 ns t w(mch) pulse duration, master clock high 20 2 15 2 ns 2 values derived from characterization data and not tested. memory and peripheral interface timing switching characteristics over recommended operating conditions tms320c15/e15/p15 TMS320C15-25/e15-25 min nom max min nom max t d1 delay time, clkout to address bus valid 10 2 50 10 3 40 ns t d2 delay time, clkout to men 1/4t c (c) 5 2 1/4t c(c) +15 1/4t c(c) 5 2 1/4t c(c) +12 ns t d3 delay time, clkout to men 10 2 15 10 2 12 ns t d4 delay time, clkout to den 1/4t c(c) 5 2 1/4t c(c) +15 1 / 4 t c(c) 5 2 1/ 4 t c(c) +12 ns t d5 delay time, clkout to den 10 2 15 10 2 12 ns t d6 delay time, clkout to we 1/2t c(c) 5 2 1/2t c(c) +15 1/2t c(c) 5 2 1/2t c(c) +12 ns t d7 delay time, clkout to we 10 2 15 10 2 12 ns t d8 delay time, clkout to data bus out valid 1/4t c(c) +65 1/4t c(c) +52 ns t d9 time after clkout that data bus starts to be driven 1/4t c(c) 5 2 1/4t c(c) 5 2 ns t d10 time after clkout that data bus stops being driven (tms320c15/c15-25 only) 1/4t c(c) + 40 2 1/4t c(c) + 40 2 ns t d10 time after clkout that data bus stops being driven (tms320e15/e15-25 only) 1/4t c(c) + 70 2 1/4t c(c) +70 2 ns t v data bus out valid after clkout 1/4t c(c) 10 1/4t c(c) 10 ns t h(a-wmd) address hold time after we , men , or den (see note 15) 0 2 2 2 0 2 2 2 ns t su(a-md) address bus setup time prior to den 1/4t c(c) 45 1/4t c(c) 35 ns 2 values derived from characterization data and not tested. note 14: address bus will be valid upon we , men , or den . timing requirements over recommended operating conditions tms320c15/e15/p15 TMS320C15-25/e15-25 min nom max min nom max t su(d) setup time, data bus valid prior to clkou- t 50 40 ns t h(d) hold time, data bus held valid after clkout (see note 9) 0 0 ns note 9: data may be removed from the data bus upon men or den preceding clkout .
r l = 825 w , c l = 100 pf (see figure 2) unit unit unit tms320c15, tms320e15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 59 reset (rs ) timing switching characteristics over recommended operating conditions parameter test conditions min typ max unit t d11 delay time, den , we , and men from rs 1/ 2 t c(c) + 50 2 ns t dis(r) data bus disable time after rs 1/ 4 t c(c) + 50 2 ns 2 values derived from characterization data and not tested. timing requirements over recommended operating conditions tms320c15/e15/p15 TMS320C15-25/e15-25 min nom max min nom max t su(r) reset (rs ) setup time prior to clkout (see note 10) 50 40 ns t w(r) rs pulse duration 5t c(c) 5t c(c) ns note 10: rs can occur anytime during a clock cycle. time given is minimum to ensure synchronous operation. interrupt (int ) timing timing requirements over recommended operating conditions tms320c15/e15/p15 TMS320C15-25/e15-25 min nom max min nom max t f(int) fall time, int 15 15 ns t w(int) pulse duration, int t c(c) t c(c) ns t su(int) setup time, int before clkout 50 40 ns io (bio ) timing timing requirements over recommended operating conditions tms320c15/e15/p15 TMS320C15-25/e15-25 min nom max min nom max t f(io) fall time, bio 15 15 ns t w(io) pulse duration, bio t c(c) t c(c) ns t su(io) setup time, bio before clkout 50 40 ns
tms320c15, tms320e15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 60 timing diagrams timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. clock timing t r(mc) t c(mc) t w(mch) t w(mcp) 2 t f(mc) t w(mcl) t d(mcc) 2 t w(ch) t w(cl) t r(c) t c(c) t f(c) x2/clkin clkout 2 t d(mcc) and t w(mcp) are referenced to an intermediate level of 1.5 v on the clkin waveform. memory read timing t c(c) t d3 t d2 t d1 t h(a-wmd) t su(d) t h(d) address bus valid t su(a-md) instruction valid clkout men a11-a0 d15-d0
tms320c15, tms320e15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 61 tblr instruction timing clkout men a11-a0 d15-d0 12 3 4 5678 t d2 t d3 t d3 t su(d) t h(d) t d1 9101112 legend: 1. tblr instruction prefetch 7. address bus valid 2. dummy prefetch 8. address bus valid 3. data fetch 9. instruction valid 4. next instruction prefetch 10. instruction valid 5. address bus valid 11. data input valid 6. address bus valid 12. instruction valid tblw instruction timing clkout men a11-a0 we d15-d0 12 3 4567 891011 t d6 t d7 t d8 t v t d9 t d10 legend: 1. tblw instruction prefetch 7. address bus valid 2. dummy prefetch 8. instruction valid 3. next instruction prefetch 9. instruction valid 4. address bus valid 10. data output valid 5. address bus valid 11. instruction valid 6. address bus valid
tms320c15, tms320e15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 62 in instruction timing clkout men a11-a0 den d15-d0 t su(d) t h(d) t su(a-md) t d5 t d4 12 345 678 legend: 1. in instruction prefetch 5. address bus valid 2. next instruction prefetch 6. instruction valid 3. address bus valid 7. data input valid 4. peripheral address valid 8. instruction valid out instruction timing clkout men a11-a0 we d15-d0 12 34 5 678 t d6 t d7 t v t d9 t d10 t d8 legend: 1. in instruction prefetch 5. address bus valid 2. next instruction prefetch 6. instruction valid 3. address bus valid 7. data output valid 4. peripheral address valid 8. instruction input valid
tms320c15, tms320e15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 63 reset timing t su(r) t su(r) t w(r) t dis(r) t d11 clkout rs den we men d15-d0 men address bus see note e data shown relative to we data in from pc addr 0 data in from pc addr pc+1 ab = address bus ab = pc ab = pc+1 ab = pc = 0 ab = pc+1 notes: a. rs forces den , we , and men high and places data bus d0 through d15 in a high-impedance state. ab outputs (and program count- er) are synchronously cleared to zero after the next complete clk cycle from rs . b. rs must be maintained for a minimum of five clock cycles. c. resumption of normal program will commence after one complete clk cycle from rs . d. due to the synchronization action on rs , time to execute the function can vary dependent upon when rs or rs occur in the clk cycle. e. diagram shown is for definition purpose only. den , we , and men are mutually exclusive. f. during a write cycle, rs may produce an invalid write address. interrupt timing clkout t su(int) t w(int) t f(int) int bio timing clkout bio t su(io) t w(io) t f(io)
tms320e15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 64 absolute maximum ratings over specified temperature range (unless otherwise noted) 2 supply voltage range, v pp (see note 6) 0.6 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating condit ionso section of this specification is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliabi lity. note 6: all voltage values are with respect to v ss . recommended operating conditions min nom max unit v pp supply voltage (see note 11) 12.25 12.5 12.75 v note 11: v pp can be applied only to programming pins designed to accept v pp as an input. during programming the total supply current is i pp + i cc . electrical characteristics over specified temperature range (unless otherwise noted) parameter test conditions min typ 3 max unit i pp1 v pp supply current v pp = v cc 5.5 v 100 v i pp2 v pp supply current (during program pulse) v pp = 12.75 v 30 50 v 3 all typical values except for i cc are at v cc = 5 v, t a = 25 c. recommended timing requirements for programming, t a = 25 c, v cc = 6, v pp = 12.5 v, (see note 13) min nom max unit t w(ipgm) initial program pulse duration 0.95 1 1.05 ms t w(fpgm) final pulse duration 3.8 63 ms t su(a) address setup time 2 m s t su(e) e setup time 2 m s t su(g) g setup time 2 m s t dis(g) output disable time from g (see note 15) 0 130 ns t en(g) output enable time from g 0 150 ns t su(d) data setup time 2 m s t su(vpp) v pp setup time 2 m s t su(vcc) v cc setup time 2 m s t h(a) address hold time 0 m s t h(d) data hold time 2 m s values derived from characterization data and not tested. notes: 13. for all switching characteristics and timing measurements, input pulse levels are 0.4 v to 2.4 v and v pp = 12.5 v 0.5 v during programming. 15. common test conditions apply for t dis(g) except during programming.
tms320e15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 65 programming the tms320e15/p15 eprom cell e15/p15 devices include a 4k 16-bit industry-standard eprom cell for prototyping, early field testing, and low-volume production. in conjunction with this eprom, the e15/p15 with a 4k-word masked rom, then, provide more migration paths for cost-effective production. eprom adapter sockets are available that provide pin-to-pin conversions for programming any e15/p15 devices. one adapter socket (part number rtc/pgm320c-06), shown in figure 8, converts a 40-pin dip device into an equivalent 28-pin device. another socket (part number rtc/pgm320a-06), not shown, permits 44- to 28-pin conversion. figure 8. eprom adapter socket (40-pin to 28-pin dip conversion) key features of the eprom cell include the normal programming operation as well as verification. the eprom cell also includes a code protection feature that allows code to be protected against copyright violations. the e15/p15 eprom cell is programmed using the same family and device pinout codes as the tms27c64 8k 8-bit eprom. the tms27c64 eprom series are unltraviolet-light erasable, electrically programmable, read-only memories, fabricated using hvcmos technology. they are pin-compatible with existing 28-pin roms and eproms. these eproms operate from a single 5-v supply in the read mode; however, a 12.5-v supply is needed for programming. all programming signals are ttl level. for programming outside the system, existing eprom programmers can be used. locations may be programmed singly, in blocks, or at random. figure 9 shows the wiring conversion to program the e15/p15 using the 28-pin pinout of the tms27c64. table 5 on pin nomenclature provides a description of the tms27c64 pins. the code to be programmed into the device should be in serial mode. the e15/p15 devices use 13 address lines to address 4k-word memory in byte format.
tms320e15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 66 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v pp a12 a7 a6 a5 a4 a3 a2 a1 a0 q1 q2 q3 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a1 a0(lsb) vpp rs ept clkin gnd q1(lsb) q2 q3 q4 q5 q6 q7 q8(msb) 40 39 38 37 36 35 34 33 32 30 29 28 27 26 25 24 23 22 21 31 a2 a3 a4 a5 a6 a7 a8 v cc a9 a10 a11 (msb)a12 e g pgm tms320e15/p15 tms27c64 pinout tms27c64 pinout 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc pgm ept a8 a9 a11 g a10 e q8 q7 q6 q5 q4 3.9 k w caution although acceptable by some eprom programmers, the signature mode cannot be used on any e1x device. the signature mode will input a high-level voltage (12.5 v dc ) onto pin a9. since this pin is not designed for high voltage, the cell will be damaged. to prevent an accidental application of voltage, texas instruments has inserted a 3.9 k w resistor between pin a9 of the ti programmer socket and the programmer itself. pin nomenclature (tms320e15/p15) name i/o definition a0-a12 i on-chip eprom programming address lines clkin i clock oscillator input e i eprom chip select ept i eprom test mode select g i eprom read/verify select gnd i ground pgm i eprom write/program select q1-q8 i/o data lines for byte-wide programming of on-chip 8k bytes of eprom rs i reset for initializing the device v cc i 5-v power supply v pp i 12.5-v power supply figure 9. tms320e15/p15 eprom programming conversion to tms27c64 eprom pinout
tms320e15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 67 table 5 shows the programming levels required for programming, verifying, reading, and protecting the eprom cell. table 5. tms320e15/p15 programming mode levels signal name tms320e15 pin tms27c64 pin program verify read protect verify eprom protect e 25 20 v il v il v il v il v ih g 24 22 v ih pulse pulse v il v ih pgm 23 27 pulse v ih v ih v ih v ih v pp 3 1 v pp v pp v cc v cc + 1 v pp v cc 30 28 v cc v cc v cc v cc + 1 v cc + 1 v ss 10 14 v ss v ss v ss v ss v ss clkin 8 14 v ss v ss v ss v ss v ss rs 4 14 v ss v ss v ss v ss v ss ept 5 26 v ss v ss v ss v pp v pp q1-q8 11-18 11-13, 15-19 d in q out q out q8=rbit q8=pulse a0-a3 2, 1, 40, 39 10-7 addr addr addr x x a4 38 6 addr addr addr x v ih a5 37 5 addr addr addr x x a6 36 4 addr addr addr v il x a7-a9 35, 34, 29 3, 25, 24 addr addr addr x x a10-a12 28-26 21, 23, 2 addr addr addr x x legend: v ih = ttl high level; v il = ttl low level; addr = byte address bit v pp = 12.5 v 0.25 v; v cc = 5 v 0.25 v; x = don't care pulse = low-going ttl level pulse; d in = byte to be programmed at addr q out = byte stored at addr; rbit = rom protect bit. programming since every memory bit in the cell is a logic 1, the programming operation reprograms certain bits to 0. once programmed, these bits can only be erased using ultraviolet light. the correct byte is placed on the data bus with v pp set to the 12.5 v level. the pgm pin is then pulsed low to program in the zeros. erasure before programming, the device must be erased by exposing it to ultraviolet light. the recommended minimum exposure dose (uv-intensity exposure-time) is 15 w ? s/cm 2 . a typical 12-mw/cm 2 , filterless uv lamp will erase the device in 21 minutes. the lamp should be located about 2.5 cm above the chip during erasure. after exposure, all bits are in the high state. verify/read to verify correct programming, the eprom cell can be read using either the verify or read line definitions shown in table 5, assuming the inhibit bit has not been programmed. program inhibit programming may be inhibited by maintaining a high level input on the e pin or pgm pin. read the eprom contents may be read independent of the programming cycle, provided the rbit (rom protect bit) has not been programmed. the read is accomplished by setting e to zero and pulsing g low. the contents of the eprom location selected by the value on the address inputs appear on q8-q1.
tms320e15, tms320p15 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 68 output disable during the eprom programming process, the eprom data outputs may be disabled, if desired, by establishing the output disable state. this state is selected by setting g and e pins high. while output disable is selected, q8-q1are placed in the high-impedance state. eprom protection to protect the proprietary algorithms existing in the code programmed on-chip, the ability to read or verify code from external accesses can be completely disabled. programming the rbit disables external access of the eprom cell and disables the microprocessor mode, making it impossible to access the code resident in the eprom cell. the only way to remove this protection is to erase the entire eprom cell, thus removing the proprietary information. the signal requirements for programming this bit are shown in table 5. the cell can be determined as protected by verifying the programming of the rbit shown in the table. standard programming procedure before programming, the device must first be completely erased. then the device can be programmed with the correct code. it is advisable to program unused sections with zeroes as a further security measure. after the programming is complete, the code programmed into the cell should be verified. if the cell passes verification, the next step is to program the rom protect bit (rbit). once the rbit programming is verified, an opaque label should be placed over the window to protect the eprom cell from inadvertent erasure by ambient light. at this point, the programming is complete, and the device is ready to be placed into its destination circuit. program cycle timing a12-a0 q8-q1 v pp v cc e pgm g program verify address stable address n+1 data in stable data out valid t su(a) t h(a) t su(d) t su(vpp) t dis(g) t su(vcc) t su(e) t h(d) t w(ipgm) t w(fpgm) t su(g) t en(g) v ih v il v ih /v oh v il /v ol v pp v cc v cc +1 v cc v ih v il v ih v il v ih v il hi-z
high-level input voltage v ih operating free-air temperature t a v oh high-level output voltage i oz off-state ouput current i i input current c i input capacitance c o output capacitance f = 1 mhz, all other pins 0 v m a m a pf pf tms320lc15 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 69 absolute maximum ratings over specified temperature range (unless otherwise noted) 2 supply voltage range, v cc (see note 6) 0.3 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range 0.3 v to v cc + 0.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range 0.3 v to v cc + 0.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous power dissipation 75 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . air temperature range above operating devices: l version 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a version 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range 55 c to +150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating condit ionso section of this specification is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliabi lity. note 6: all voltage values are with respect to v ss . recommended operating conditions min nom max unit v cc supply voltage 3.0 3.3 3.6 v v ss supply voltage 0 v all inputs except clkin 2.0 v clkin 2.5 v v il low-level input voltage all inputs 0.55 v i oh high-level output current (all outputs) 300 m a i ol low-level output current (all outputs) 1.5 ma l version 070 c a version 40 85 c electrical characteristics over specified temperature range (unless otherwise noted) parameter test conditions min typ 2 max unit i oh = max 2.0 v i oh = 20 m a (see note 7) v cc 0.4 3 v v ol low-level output voltage i ol = max 0.5 v v cc = max, v o = v cc 20 v o = v ss 20 v i = v ss to v cc all inputs except clkin 20 v i = v ss to v cc clkin 50 data bus 25 3 all others 15 3 data bus 25 3 all others 10 3 2 all typical values are at v cc = 3.3 v, t a = 25 c. 3 values derived from characterization data and not tested. note 7: this voltage specification is included for interface to hc logic. however, note that all of the other timing parameters defined in this data sheet are specified for ttl logic levels and will differ for hc logic levels.
tms320lc15 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 70 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a1/pa1 a0/pa0 mc/mp rs int clkout x1 x2/clkin bio v ss d8 d9 d10 d11 d12 d13 d14 d15 d7 d6 a2/pa2 a3 a4 a5 a6 a7 a8 men den we v cc a9 a10 a11 d0 d1 d2 d3 d4 d5 n package (top view) clkout x1 x2/clkin bio nc v ss d8 d9 d10 d11 d12 a7 a8 men den we v cc a9 a10 a11 d0 d1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 int rs mc/mp a0/pa0 a1/pa1 a2/pa2 a3 a4 a5 a6 d13 d14 d15 d7 d6 d5 d4 d3 d2 fn package (top view) ss v ss v ss v internal clock option c1 c2 crystal x1 x2/clkin 320lc15 parameter measurement information 1.75 v from output under test r l = 825 w test point c l = 100 pf figure 10. test load circuit
t a = 40 c to 85 c tms320lc15 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 71 clock characteristics and timing the lc15 can use either its internal oscillator or an external frequency source for a clock. internal clock option the internal oscillator is enabled by connecting a crystal across x1 and x2/clkin (see figure 1). the frequency of clkout is one-fourth the crystal fundamental frequency. the crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mw, and be specified at a load capacitance of 20 pf. parameter test conditions min nom max unit crystal frequency f x 4.0 16 mhz c1, c2 10 pf external clock option an external frequency source can be used by injecting the frequency directly into x2/clkin with x1 left unconnected. the external frequency injected must conform to the specifications listed in the table below. switching characteristics over recommended operating conditions parameter test conditions min nom max unit t c(c) clkout cycle time 2 250 1000 ns t r(c) clkout rise time r l = 825 w , 10 3 ns t f(c) clkout fall time c l = 100 pf, 8 3 ns t w(cl) pulse duration, clkout low (see figure 2) 117 3 ns t w(ch) pulse duration, clkout high 115 3 ns t d(mcc) delay time, clkin to clkout 20 70 ns timing requirements over recommended operating conditions min nom max unit t c(mc) master clock cycle time 62.5 150 ns t r(mc) rise time, master clock input 5 3 10 2 ns t f(mc) fall time, master clock input 5 3 10 2 ns t w(mcp) pulse duration, master clock 0.4 t c(mc) 3 0.6 t c(mc) 3 ns t w(mcl) pulse duration, master clock low at t c(mc) min 26 ns t w(mch) pulse duration, master clock high at t c(mc) min 26 ns 2 t c(c) is the cycle time of clkout, i.e., 4t c(mc) (4 times clkin cycle time if an external oscillator is used) 3 values derived from characterization data and not tested.
tms320lc15 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 72 electrical characteristics over specified temperature range (unless otherwise noted) parameter test conditions min typ 2 max unit i cc 3 f = 16.0 mhz, v cc = 3.6 v, t a = 0 c to 70 c 15 20 ma 2 all typical values are at t a = 70 c and are used for thermal resistance calculations. 3 i cc characteristics are inversely proportional to temperature. for i cc dependence on frequency, see figure below. typical power vs. frequency graph (outputs unloaded) 20.0 15.0 10.0 5.0 0.0 (ma) i cc clkin frequency, mhz 40 c to 85 c temperature range 2468 10 12 14 v cc = 3.5 v v cc = 3 v 0 16 device operation is not guaranteed below 4 mhz clkin. graph is for device in reset; i.e., only clock-out is driven.
r l = 825 w , c l = 100 pf, (see figure 2) r l = 825 w , c l = 100 pf, (see figure 2) tms320lc15 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 73 memory and peripheral interface timing switching characteristics over recommended operating conditions parameter test conditions min max unit t d1 delay time clkout to address bus valid 10 2 75 n s t d2 delay time clkout to men 1/4 t c(c) 5 2 1/4 t c(c) +25 ns t d3 delay time clkout to men 10 2 30 ns t d4 delay time clkout to den 1/4 t c(c) 5 2 1/4 t c(c) +25 ns t d5 delay time clkout to den 102 30 ns t d6 delay time clkout to we 1/2 t c(c) 5 2 1/2 t c(c) +25 ns t d7 delay time clkout to we 10 2 30 ns t d8 delay time clkout to data bus out valid 1/4 t c(c) +75 ns t d9 time after clkout that data bus starts to be driven 1/4 t c(c) 5 2 ns t d10 time after clkout that data bus stops being driven 1/4 t c(c) +60 ns t v data bus out valid after clkout 1/4 t c(c) 10 ns t h(a-wmd) address hold time after we , men , or den (see note 14) 0 2 ns t su(a-md) address bus setup time to den 4 2 ns 2 values derived from characterization data and not tested. note 14: address bus will be valid upon we , men , or den . timing requirements over recommended operating conditions test conditions min nom max unit t su(d) setup time data bus valid prior to clkout 56 ns t h(d) hold time, data bus held valid after clkout (see note 9) 0 ns note 9: data may be removed from the data bus upon men or den preceding clkout .
r l = 825 w , c l = 100 pf, (see figure 2) tms320lc15 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 74 reset (rs ) timing switching characteristics over recommended operating conditions test conditions min nom max unit t d11 delay time, den , we , and men from rs 1/2t c(c) +75 ns t dis(r) data bus disable time after rs 1/4t c(c) +75 ns 2 these parameters do not apply to this device. timing requirements over recommended operating conditions min nom max unit t su(r) reset (rs ) setup time prior to clkout (see note 10) 85 ns t w(r) rs pulse duration 5t c(c) ns note 10: rs can occur anytime during a clock cycle. time given is minimum to ensure synchronous operation. interrupt (int ) timing timing requirements over recommended operating conditions min nom max unit t f(int) fall time, int 15 ns t w(int) pulse duration, int t c(c) ns t su(int) setup time, int before clkout 85 ns i/o (bio ) timing timing requirements over recommended operating conditions min nom max unit t f(io) fall time bio 15 ns t w(io) pulse duration bio t c(c) ns t su(io) setup time bio before clkout 85 ns
tms320lc15 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 75 clock timing t r(mc) t c(mc) t w(mch) t w(mcp) 2 t f(mc) t w(mcl) t d(mcc) 2 t w(ch) t w(cl) t r(c) t c(c) t f(c) x2/clkin clkout 2 t d(mcc) and t w(mcp) are referenced to an intermediate level of 1.5 v on the clkin waveform. in instruction timing clkout men pa2-pa0 den d15-d0 t su(d) t h(d) t su(a-md) t d5 t d4 12 345 678 legend: 1. in instruction prefetch 5. address bus valid 2. next instruction prefetch 6. instruction valid 3. address bus valid 7. data input valid 4. peripheral address valid 8. instruction valid
tms320lc15 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 76 out instruction timing clkout men pa2-pa0 we d15-d0 12 34 5 678 t d6 t d7 t d8 t v t d9 t d10 legend: 1. out instruction prefetch 5. address bus valid 2. next instruction prefetch 6. instruction valid 3. address bus valid 7. data output valid 4. peripheral address valid 8. instruction valid external memory read timing t c(c) t d3 t d2 t d1 t h(a-wmd) t su(d) t h(d) address bus valid t su(a-md) instruction valid clkout men a11-a0 d15-d0
tms320lc15 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 77 tblr instruction timing clkout men a11-a0 d15-d0 12 3 4 5678 t d2 t d3 t d3 t su(d) t h(d) t d1 9101112 legend: 1. tblr instruction prefetch 7. address bus valid 2. dummy prefetch 8. address bus valid 3. data fetch 9. instruction valid 4. next instruction prefetch 10. instruction valid 5. address bus valid 11. data input valid 6. address bus valid 12. instruction valid tblw instruction timing clkout men a11-a0 we d15-d0 12 3 4567 891011 t d6 t d7 t d8 t v t d10 t d9 legend: 1. tblw instruction prefetch 7. address bus valid 2. dummy prefetch 8. instruction valid 3. next instruction prefetch 9. instruction valid 4. address bus valid 10. data output valid 5. address bus valid 11. instruction valid 6. address bus valid
tms320lc15 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 78 reset timing t su(r) t su(r) t w(r) t dis(r) t d11 clkout rs den we men d15-d0 men address bus (see note e) data shown relative to we data in from pc addr 0 data in from pc addr pc+1 ab = address bus ab = pc ab = pc+1 ab = pc = 0 ab = pc+1 notes: a. rs forces den , we , and men high and places data bus d0 through d15 in a high-impedance state. ab outputs (and program count- er) are synchronously cleared to zero after the next complete clk cycle from rs . b. rs must be maintained for a minimum of five clock cycles. c. resumption of normal program will commence after one complete clk cycle from rs . d. due to the synchronization action on rs , time to execute the function can vary dependent upon when rs or rs occur in the clk cycle. e. diagram shown is for definition purpose only. den , we , and men are mutually exclusive. f. during a write cycle, rs may produce an invalid write address. interrupt timing clkout t su(int) t w(int) t f(int) int bio timing clkout bio t su(io) t w(io) t f(io)
data (16) address (12) 256-word ram 8k-word rom 32-bit alu/acc multiplier shifters interrupt +5 v gnd 8-level stack nc nc a0/pa0 a1/pa1 a2/pa2 a3 a4 a5 a6 v ss a7 a8 a9 a10 a11 a12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 a13 a14 nc nc rs x1 x2/clkin v ss v ss v ss v ss clkout d15 d14 nc d13 d12 d11 d10 d9 nc nc 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 d8 d7 d6 d5 d4 d3 d2 nc d1 d0 a15 nc bio int mc/mp v v v men nc ioen mwe iowe v dd dd dd dd v dd v ss pg package (top view) tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 79 key features: tms320c16 ? 114-ns instruction cycle time ? 256 words of on-chip data ram ? 8k words of on-chip program rom ? 64k words total external memory at full speed ? 8 level stack ? 32-bit alu/accumulator ? 16 16-bit multiplier with 32-bit product ? 16-bit barrel shifter ? eight input and eight output channels ? simple memory and i/o interface: e memory write enable signal mwe e i/o write enable signal iowe ? single 5-v supply ? 64-pin quad flatpack (pg suffix) ? operating free-air temperature range ...0 c to 70 c
i/o/z 2 tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 80 terminal functions pin description name no. address/data buses a15 msb a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2/pa2 a1/pa1 a0/pa0 32 34 35 36 37 38 39 40 41 43 44 45 46 47 48 49 i/o/z program memory address bus a15 (msb) through a0 (lsb) and port addresses pa2 (msb) through pa0 (lsb). addresses a15 through a0 are always active and never go to high impedance. during execution of the in and out instructions, pins a2 through a0 carry the port addresses. (address pins a15 through a3 are always driven low on in and out instruction. d15 msb d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lsb 10 11 13 14 15 16 17 20 21 22 23 25 27 28 30 31 i/o/z parallel data bus d15 (msb) through d0 (lsb). the data bus is always in the high-impedance state except when iowe or mwe are active (low). 2 input/output/high-impedance state.
i/o/z 2 description i/o/z 2 tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 81 terminal functions (concluded) pin description name no. interrupt and miscellaneous signals bio 64 i external polling input. polled by bioz instruction. if low, the device branches to the address specified by the instruction. ioen 54 o data enable for device input data. when active (low), ioen indicates that the device will accept data from the data bus. ioen is active only during the in instruction. when ioen is active, men , iowe , and mwe will always be inactive (high). iowe 52 o write enable for device output data. when active (low), iowe indicates that data will be output from the device on the data bus. iowe is active only during the out instruction. when iowe is active, men , ioen , and mwe will always be inactive (high). int 63 i external interrupt input. the interrupt signal is generated by applying a negative-going edge to the int pin. the edge is used to latch the interrupt flag register (intf) until an interrupt is granted by the device. an active low level will also be sensed. mc/mp 62 i memory mode select pin. high selects the microcomputer mode, in which 8k words of on-chip program memory are available. a low on mc/mp pin enables the microprocessor mode. in this mode, the entire memory space is external; i.e., addresses 0 through 65535. men 56 o memory enable. men is an active (low) control signal generated by the device to enable instruction fetches from program memory. men will be active on instructions fetched from both internal and external memory. when men is active, mwe , iowe , and ioen will be inactive (high). mwe 53 o write enable for device output data. when active (low), mwe indicates that data will be output from the device on the data bus. mwe is active only during the tblw instruction. when mwe is active, men , ioen , and iowe will always be inactive (high). nc 1, 12, 18, 19, 24, 29, 33, 50, 51, 55 e no connection. rs 2 i schmitt-triggered input for initializing the device. when held active for a minimum of five clock cycles. ioen , iowe , mwe , and men are forced high; and, the data bus (d15 through d0) is not driven. the program counter (pc) and the address bus (a15 through a0) are then synchronously cleared after the next complete clock cycle from the falling edge of rs . reset also disables the interrupt, clears the interrupt flag register, and leaves the overflow mode register unchanged. the device can be held in the reset state indefinitely. supply/oscillator signals pin name no. clkout 9 o system clock output (one-fourth crystal/clkin frequency). v dd 26, 57, 58, 59, 60 i 5-v suppy pins. v ss 5, 6, 7, 8, 42, 61 i ground pins. x1 3 o crystal output pin for internal oscillator. if the internal oscillator is not used, this pin should be left unconnected. x2/clkin 4 i input pin to the internal oscillator (x2) from the crystal. alternatively, an input pin for an external oscillator (clkin). 2 input/output/high-impedance state.
tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 82 functional block diagram 16 d15-d0 32 16 16 16 32 shifter (0,1,4) 32 acc (32) 32 alu (32) data ram (256 words) address data 32 32 mux 32 16 p(32) t(16) multiplier shifter (016) 16 8 dp 7 mux 8 8 ar1 (16) ar0 (16) arp 16 16 data bus data bus 16 16 16 program bus a15-a0/ pa2-pa0 16 instruction program rom (8k words) 3 int mc/mp bio men iowe mwe ioen stack 8 16 16 pc (16) 16 lsb mux 16 program bus x2/clkin clkout x1 controller mux address legend: acc= accumulator arp = auxiliary register pointer ar0 = auxiliary register 0 ar1 = auxiliary register 1 dp = data page pointer p = p register pc = program counter t = t register mux rs 16
v ih high-level input voltage v il low-level input voltage v m a m a pf pf v oh high-level output voltage i oz off-state output current c i input capacitance i i input current c o output capacitance f = 1 mhz, all other pins 0 v v cc = v ss to v cc v cc = max tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 83 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v cc (see note 6) 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous power dissipation 0.5 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature: 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating condit ionso section of this specification is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliabi lity. note 6: all voltage values are with respect to v ss. recommended operating conditions min nom max unit v cc supply voltage 4.75 5 5.25 v v ss supply voltage 0 v all inputs except clkin 2 v clkin 3 v all inputs except mc/mp 0.8 v mc/mp 0.6 v i oh high-level output current, all outputs 300 m a i ol low-level output current 2 ma t a operating free-air temperature 0 70 c electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit i oh = max 2.4 3 i oh = 20 m a v cc 0.4 v ol low-level output voltage i ol = max 0.3 0.5 v v o = 2.4 v 20 v o = 0.4 v 20 all inputs except clkin 20 clkin 50 i cc supply current f = 35 mhz, v cc = 5.25 v 60 75 ma data bus 25 all others 15 data bus 25 all others 10
tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 84 internal clock option parameter test conditions min nom max unit crystal frequency, f x t a = 0 c to 70 c 6.7 35.1 mhz c1, c2 t a = 0 c to 70 c 10 pf timing requirements over recommended operating conditions min nom max unit t c(mc) master clock cycle time 28.49 28.57 150 ns t r(mc) rise time, master clock input 5 10 ns t f(mc) fall time, master clock input 5 10 ns t w(mcp) pulse duration, master clock 0.45t c(c) 0.55t c(c) ns t w(mcl) pulse duration, master clock low 10 ns t w(mch) pulse duration, master clock high 10 ns switching characteristics over recommended operating conditions parameter min nom max unit t c(c) clkout cycle time 113.96 114.3 600 ns t r(c) clkout rise time 10 ns t f(c) clkout fall time 8 ns t w(cl) pulse duration, clkout low 49 ns t w(ch) pulse duration, clkout high 47 ns t d(mcc) delay time, clkin to clkout 5 50 ns
tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 85 memory and peripheral interface timing switching characteristics over recommended operating conditions parameter min nom max unit t d1 delay time, men , mwe , ioen , iowe , to next address bus valid 0 35 ns t d2 delay time, clkout to men 1 / 4 t c(c) 5 1 / 4 t c(c) +12 ns t d3 delay time, clkout to men 3 6 ns t d4 delay time, clkout to ioen 1 / 4 t c(c) 5 1 / 4 t c(c) +12 ns t d5 delay time, clkout to ioen 3 6 ns t d6 delay time, clkout to mwe , iowe 1 / 2 t c(c) 5 1 / 2 t c(c) +12 ns t d7 delay time, clkout to mwe , iowe 3 6 ns t d8 delay time, mwe , iowe , data bus out valid 0 ns t d9(clk) delay time, clkout to data bus starts to be driven 1 / 4 t c(c) 5 ns t d9(men) delay time, men , to data bus starts to be driven 1 / 4 t c(c) ns t d10(clk) delay time, clkout to data bus stops being driven 15 ns t d10(we) delay time, mwe , iowe , data bus stops being driven 20 ns t v data bus out valid after mwe , iowe 5 10 ns t h(a-wmd) address bus hold time after mwe , men , iowe , or ioen 0 2 ns t su(a-md) address bus setup time prior to men , ioen 5 ns timing requirements over recommended operating conditions min max unit t su(d) setup time, data bus valid prior to men , ioen 35 ns t h(d) hold time, data bus held valid after men , ioen 0 ns reset (rs ) timing switching characteristics over recommended operating conditions parameter min max unit t d11 delay time, ioen , iowe , mwe , and men from rs 1 / 2 t c(c) +50 ns t dis(r) data bus disable time after rs 1 / 4 t c(c) +50 ns timing requirements over recommended operating conditions min max unit t su(r) reset (rs ) setup time prior to clkout 30 ns t w(r) rs pulse duration 5t c(c) ns
tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 86 interrupt (int ) timing timing requirements over recommended operating conditions min max unit t f(int) fall time, int 15 ns t w(int) pulse duration, int t c(c) ns t su(int) setup time, int before clkout 30 ns io (bio ) timing timing requirements over recommended operating conditions min max unit t f(io) fall time, bio 15 ns t w(io) pulse duration, bio t c(c) ns t su(io) setup time, bio before clkout 30 ns timing diagrams timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. clock timing t r(mc) t c(mc) t w(mch) t w(mcp) 2 t f(mc) t w(mcl) t d(mcc) 2 t w(ch) t w(cl) t r(c) t c(c) t f(c) x2/clkin clkout 2 t d(mcc) and t w(mcp) are referenced to an intermediate level of 1.5 v on the clkin waveform.
tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 87 memory read timing t c(c) t d3 t d2 t d1 t h(a-wmd) t su(d) t h(d) t su(a-md) instruction input valid clkout men a15-a0 d15-d0 address bus valid in instruction timing clkout men a15-a0 ioen d15-d0 t su(d) t h(d) t su(a-md) t d5 12 345 678 t d4 legend: 1. in instruction prefetch 5. address bus valid 2. next instruction prefetch 6. instruction input valid 3. address bus valid 7. data input valid 4. peripheral address valid 8. instruction input valid
tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 88 out instruction timing clkout men a15-a0 iowe d15-d0 6 7 8 t d7 t d9(men) t v t d9(clk) t d6 t d8 t d10(we) t d10(clk) 12 345 legend: 1. out instruction prefetch 5. address bus valid 2. next instruction prefetch 6. instruction valid 3. address bus valid 7. data output valid 4. peripheral address valid 8. instruction valid tblr instruction timing clkout men a15-a0 d15-d0 t d2 t d3 t su(d) t h(d) t d1 tblw instruction timing clkout men a15-a0 mwe d15-d0 6 7 8 t d7 t d9(men) t v t d9(clk) t d6 t d8 t d10(we) t d10(clk)
tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 89 reset timing t su(r) t su(r) t w(r) t dis(r) t d11 clkout rs ioen , iowe men , mwe d15-d0 men address bus (see note e) data shown relative to iowe data in from pc addr 0 data in from pc addr pc+1 ab = address bus ab = pc ab = pc+1 ab = pc = 0 ab = pc+1 data out notes: a. rs forces ioen , iowe , mwe , and men high and places data bus d0 through d15 in a high-impedance state. ab outputs (and program counter) are synchronously cleared to zero after the next complete clk cycle from rs . b. rs must be maintained for a minimum of five clock cycles. c. resumption of normal program will commence after one complete clk cycle from rs . d. due to the synchronization action on rs , time to execute the function can vary dependent upon when rs or rs occur in the clk cycle. e. diagram shown is for definition purpose only. ioen , iowe , mwe , and men are mutually exclusive. f. during a write cycle, rs may produce an invalid write address. interrupt timing clkout t su(int) t w(int) t f(int) int bio timing clkout bio t su(io) t w(io) t f(io)
tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 90 design considerations for interfacing to sram, eprom and peripherals the c16 differs somewhat from the other members of the c1x family of digital signal processors (dsps). additional control signals are available for easier interface to external memory or peripherals, and the memory write cycle timings have been changed. the discussion here will center around changes in t v and its impact upon sram, eprom and peripherals/latches interfaces. access time requirements for interface may be defined relative to : 1. valid address (t a ); 2. men /ioen , [(t a(men) ]; figure 11 and the following examples summarize these timings at 35 mhz clkin. t c(c) t w(ch) t d2 t a(men) t d1 t a t su(d) clkout men a15-a0 d15-d0 t a (clkout) t f(c) figure 11. where: t a : (access time from address valid) = t c(c) t d1 t su(d) = 44.3 ns t a(men) : (access time from men valid) = t c(c) t d2 t su(d) + t d3 = 35.73 ns and where (for 35 mhz clkin): t c(c) = 114.3 ns t d1 = 35 ns t d2 = [1/4 (114.3) + 12] ns t su(d) = 35 ns t w(ch) = 47 ns nominal t f(c) = 8 ns nominal
tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 91 in addition to the above timings, t v must be taken into account. t v is the time that the data bus is guaranteed to be held after the rising edge of mwe or iowe . in other c1x devices, the value of t v was referenced to clkout and not we (see figure 12). for the c16, t v is a minimum of 5 ns. this implies that mwe and iowe must be tied directly to the external device. if required, decode logic must be added to an input other than the read/write input e for example, the chip select on srams. if the external device does not have two inputs, then transparent latches must be added to extend the time data is held on the data bus. these latches must be off the bus prior to the next instruction (see figure 12). clkout mwe or iowe d15-d0 t v t d10 figure 12. where: t v = 5 ns (min) t d10 = 15 ns (max) there is a potential for bus conflict on the prefetch and execution of a tblw or an out instruction. figure 13 details the timings to be considered. in addition to the timings for the c16, timing definitions for interface are also included. t dmemh clkout men ce d15-d0 memory driven data d15-d0 dsp driven data t ddeco t d9(men) t conf tblw or out execution dummy prefetch cycle figure 13. where:
tms320c16 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 92 t conf (data bus conflict time) = t ddeco + t dmemh t d9(men) with: t ddeco : decode delay time to make the ce or oe signal t dmemh : memory data hold time from ce or oe t d9 : delay time, men to data bus starts being driven t d9 : (at 35 mhz clkin) = [1/4t c(c) ] = [1/4(114.3)] = 28.58 ns if t conf is less than or equal to zero, data bus conflict does not occur. if t conf is greater than zero, data conflict occurs. note that the following discussion is for clkin of 35 mhz. static memory with output enable and write enable/chip select the following srams are able to interface directly to the c16, needing only to directly connect the c16 memory control signals men and mwe to the memory. device select decode is accomplished with address decode and then input to the device chip select. product t ddeco t dmemh t dconf units tc55645-35 0 15 13.58 ns tc55328-35 0 15 13.58 ns tms6789-35 0 8 20.58 ns tc5588-35 0 10 18.58 ns tms6716-35 0 10 18.58 ns als138 (decoder) we oe cs addr data mwe men a15-axx d15-d0 tms320c16 sram with oe figure 14.
tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 93 static memory with chip enable and write enable without a separate output enable, a faster sram is required. logic is added to decode address and memory control to perform a read/write cycle. the mwe signal is directly connected to the we input of the sram to meet the t v specification (see figure 15). product t ddeco t dmemh t dconf units cy7c164-25 7.5 10 11.08 ns programmable logic we ce addr data mwe men a15-axx d15-d0 tms320c16 sram with ce 7.5 ns figure 15. eprom interface the following high-speed eproms can be used directly: product t ddeco t dmemh t dconf units cy7c291-35 0 25 3.58 ns tms27c291-35 0 25 3.58 ns decoder 7.5 ns cs1 cs2 cs3 data men a15-axx d15-d0 tms320c16 fast eprom tms27c291-35 addr v cc figure 16.
tms320c16 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 94 interfacing latches to the tms320c16 as with the previous devices, the memory control signal must be directly connected to the latch and the latch needs to have a separate chip select. there are several devices with this feature, including the sn74als996. the sn74als996 is an 8-bit d-type edge-triggered read-back latch with three-state outputs, connected to the c16 as illustrated in figure 17. en ioen tms320c16 als996a x 2 als 138 rd clk d15-d0 iowe d15-d0 a2 a1 a0 decoder figure 17.
data (16) address (3) dua-channel serial port coprocessor interface m -law/a-law hardware timer interrupt 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pa1/rble pa0/hi/lo mc rs exint clkout x1 x2/clkin bio v ss d8/ld8 d9/ld9 d10/ld10 d11/ld11 d12/ld12 d13/ld13 d14/ld14 d15/ld15 d7/ld7 d6/ld6 pa2/tblf fsr fsx fr dx1 dx0 sclk dri den /rd we /rd v cc dr0 xf mc/pm d0/ld0 d1/ld1 d2/ld2 d3/ld3 d4/ld4 d5/ld5 tms320c17/e17/lc17/p17 n/jd package clkout x1 x2/clkin bio nc v ss d8 d9 d10 d11 d12 dx0 sclk dr1 den/rd we/wr v cc dr0 xf mc/pm d0/ld0 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 exint rs mc pao/hi/lo pa1/rble pa2/tblf fsr fsx fr dx1 d13/ld13 d14/ld14 d15/ld15 d7/ld7 d6/ld6 d5/ld5 d4ld4 d3/ld3 d2/ld2 tms320c17, tms320e17 fn/fz packages ss v ss v d1/ld1 320c17 or 320e17 serial interface ? device packaging: e 40-pin dip (all devices) e 44-lead plcc (tms320c17/lc17/p17 e 44-lead cer-quad (tms320e17) ? 3.3 -v low-power version available (tms320lc17) ? operating free-air temperature range ...0 c to 70 c ? 16-bit coprocessor interface for common 4/8/16/32-bit microcomputers/microprocessors (top view) (top view) tms320c17, tms320e17, tms320lc17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 95 key features: tms320c17/e17/lc17/p17 ? 200-ns instruction cycle timing (tms320c17/e17/p17) ? 278-ns instruction cycle timing (tms320lc17) ? 256 words of on-chip data ram ? 4k words of on-chip program rom (tms320c17/lc17) ? 4k words of on-chip program eprom (tms320e17/p17) ? one-time programmable (otp) windowless eprom version available (tms320p17) ? eprom code protection for copyright security ? dual-channel serial port for full-duplex serial communication ? serial port timer for standalone serial communication ? on-chip companding hardware for m -law/a-law pcm conversions
tms320c17, tms320e17, tms320lc17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 96 architecture the c17/e17/lc17/p17 consists of five major functional units: the c15 microcomputer, a system control register, a full-duplex dual-channel serial port, companding hardware, and a coprocessor port. three of the i/o ports are used by the serial port, companding hardware, and the coprocessor port. their operation is determined by the 32 bits of the system control register (see table 6 for the control register bit definitions). port 0 accesses control register 0 and consists of the lower 16 register bits (cr15-cr0), and is used to control the interrupts, serial port connections, and companding hardware operation. port 1 accesses control register 1, consisting of the upper 16 control bits (cr31-cr16), as well as both serial port channels, the companding hardware, and the coprocessor port channels. communication with the control register is via in and out instructions to ports 0 and 1. interrupts fully support the serial port interface. four maskable interrupts (exint , fr, fsx , and fsr ) are mapped into i/o port 0 via control register 0. when disabled, these interrupts may be used as single-bit logic inputs polled by software. serial port the dual-channel serial port is capable of full-duplex serial communication and offers direct interface to two combo-codecs. two receive and two transmit registers are mapped into i/o port 1, and operate with 8-bit data samples. internal and external framing signals for serial port transfers (msb first) are selected via the system control register. the serial port clock, sclk, provides the bit timing for transfers with the serial port, and may be either an input or output. as an input, an external clock provides the timing for data transfers and framing pulse synchronization. as an output, sclk provides the timing for standalone serial communication and is derived from the c17/e17/p17 system clock, x2/clkin, and system control register bits cr27-cr24 (see table 7 for the available divide ratios). the internal framing (fr) pulse frequency is derived from the serial port clock (sclk) and system control register bits cr23-cr16. this framing pulse signal provides framing pulses for combo-codecs, for a sample clock for voice-band systems, or for a timer used in control applications. m -law/a-law companding hardware the c17/e17/lc17/p17 features hardware companding logic and can operate in either m -law or a-law format with either sign-magnitude or twos-complement numbers. data may be companded in either a serial mode for operation on serial port data or a parallel mode for computation inside the device. the companding logic operation is selected through cr14. no bias is required when operating in twos-complement. a bias of 33 is required for sign-magnitude in m -law companding. upon reset, the device is programmed to operate in sign-magnitude mode. this mode can be changed by modifying control bit 29 (cr29) in control register 1. for further information on companding, see the tcm29c13/tcm29c14/tcm29c16/tcm29c17 combined single-chip pcm codec and filter data sheet , and the application report, a companding routines for the tms32010/tms32020,o in the book digital signal processing applications with the tms320 family (spra012a), both documents published by texas instruments. in the serial mode, sign-magnitude linear pcm (13 magnitude bits plus 1 sign bit for m -law format or 12 magnitude bits plus 1 sign bit for a-law format) is compressed to 8-bit sign-magnitude logarithmic pcm by the encoder and sent to the transmit register for transmission on an active framing pulse. the decoder converts 8-bit sign-magnitude log pcm from the serial port receive registers to sign-magnitude linear pcm. in the parallel mode, the serial port registers are disabled to allow parallel data from internal memory to be encoded or decoded for computation inside the device. in the parallel encode mode, the encoder is enabled and a 14-bit sign-magnitude value written to port 1. the encoded value is returned with an in instruction from port 1. in the parallel decode mode, the decoder is enabled and an 8-bit sign-magnitude log pcm value is written to port 1. on the successive in instruction from port 1, the decoded value is returned. at least one instruction should be inserted between an out and the successive in when companding is performed with twos-complement values.
31302928272625242322212019181716151413121110987 654 3210 interrupt mask bits frame counter modulus fr pulse widt h port 1 port 0 reserved i/o control serial clock prescale control serial-port configuration companding hardware control interrupt flags port 1 configuration control: external framing enable: serial-port enable: m -law/a-law encoder enable: m -law/a-law decoder enable: m -law/a-law decoder encode/decoded select: serial clock control: fr pulse-width control: two's-complement m -law/a-law conversion enable: 8/16-bit length coprocessor mode select: tms320c17, tms320e17, tms320lc17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 97 table 6. control register configuration bit description and configuration 0 exint interrupt flag 2 1 fsr interrupt flag 2 2 fsx interrupt flag 2 3 fr interrupt flag 2 4 exint interrupt enable mask. when set to logic 1, an interrupt on exint activates device interrupt circuitry. 5 fsr interrupt enable mask. same as exint control. 6 fsx interrupt enable mask. same as exint control. 7 fr interrupt enable mask. same as exint control. 8 0 = port 1 connects to either serial-port registers or companding hardware. 1 = port 1 accesses cr31-cr16. 9 0 = serial-port data transfers controlled by active fr. 1 = serial-port data transfers controlled by active fsx /fsr . 10 xf external logic output flag latch 11 0 = parallel companding mode; serial port disabled. 1 = serial companding mode; serial port registers enabled. 12 0 = disabled. 1 = data written to port 1 is m -law or a-law encoded. 13 0 = disabled. 1 = data written to port 1 is m -law or a-law decoded. 14 0 = companding hardware performs m -law conversion. 1 = companding hardware performs a-law conversion. 15 0 = sclk is an output, derived from the prescaler in timing logic. 1 = sclk is an input that provides the clock for serial port and frame counter in timing logic. 23-16 frame counter modulus. controls fr frequency = sclk/(cnt + 2) where cnt is binary value fo cr23-cr16 3 27-24 sclk prescale cotnrol bits. (see table 7 for divide ratios.) 28 0 = fixed-data rate; fr is 1 sclk cycle wide. 1 = variable-data rate; fr is 8 sclk cycles wide. 29 0 = sign-magnitude companding 1 = twos-complement companding 30 0 = 8-bit byte length 1 = 16-bit word length 31 reserved for future expansion: should be set to zero. 2 interrupt flag is cleared by writing a logic 1 to the bit with an out instruction to port 0. 3 all ones in cr23-cr16 indicate a degenerative state and should be avoided. bits are operational whether sclk is an input or an output. cnt must be greater than 7.
tms320c17, tms320e17, tms320lc17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 98 table 7. serial clock (sclk) divide ratios (x2/clkin = 20.48 mhz) cr27 cr26 cr25 cr24 divide ratio sclk frequency unit 0 0 0 0 32 0.640 mhz 0 0 0 1 28 0.731 mhz 0 0 1 0 24 0.853 mhz 0 1 0 0 20 1.024 mhz 1 0 0 0 16 1.280 mhz 1 0 0 1 14 1.463 mhz 1 0 1 0 12 1.706 mhz 1 1 0 0 10 2.048 mhz the specification for m -law and a-law log pcm coding is part of the ccitt g.711 recommendation. the following diagram shows a c17/e17/p17 interface to two codecs as used for m -law or a-law companding format. dx0 dr0 sclk fr dx1 dr1 v ss v cc mc mc/pm x2 x1 +5 v pcm in pcm out clkr/x fsx fsr tcm29c13 pcm in pcm out clkr/x fsx fsr tcm29c13 analog out analog in analog out analog in tms320c17/e17/p17 coprocessor port the coprocessor port, accessed through i/o port 5 using in and out instructions, provides a direct connection to most 4/8-bit microcomputers and 16/32-bit micorprocessors. the coprocessor interface allows the c17/e17/p17 to act as a peripheral (slave) microcomputer to a microprocessor, or a master to a peripheral microcomputer such as tms7042. the coprocessor port is enabled by setting mc/pm and mc low. the microcomputer mode is enabled by setting these two pins high. (note that mc/pm mc is undefined.) in the microcomputer mode, the 16 data lines are used for the 6 parallel 16-bit i/o ports. in the coprocessor mode, the 16-bit coprocessor port is reconfigured to operate as a 16-bit latched bus interface. control bit 30 (cr30) in control register 1 is used to configure the coprocessor port to either an 8-bit or a 16-bit length. when cr30 is high, the coprocessor port is 16 bits wide thereby making all 16 bits of the data port available for 16-bit transfers to 16 and 32-bit microprocessors. when cr30 is low, the port is 8-bits wide and mapped to the low byte of the data port for interfacing to 8-bit microcomputers. when operating in the 8-bit mode, both halves of the 16-bit latch can be addressed using the hi/lo pin, thus allowing 16-bit transfers over 8 data lines. when not in the coprocessor mode, port 5 can be used as a generic i/o port.
tms320c17, tms320e17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 99 coprocessor port (continued) the external processor recognizes the coprocessor interface in which both processors run asynchronously as a memory-mapped i/o operation. the external processor lowers the wr line and places data on the bus. it next raises the wr line to clock the data into the on-chip latch. the rising edge of wr automatically creates an interrupt to the c17/e17/p17, and the falling edge of wr clears the rble (receive buffer latch empty) flag. when the c17/e17/p17 reads the coprocessor port, it causes the rble signal to transition to a logic low state that clears the data in the latch, and allows the interrupt condition to be cleared internally. likewise, the external processor reads form the latch by driving the rd line active low, thus enabling the output latch to drive the latched data. when the data has been read, the external device will again bring the rd line high. this activates the bio line to signal that the transfer is complete and the latch is available for the next transfer. the falling edge of rd resets the tblf (transmit buffer latch full) flag. note that the exint and bio lines are reserved for coprocessor interface and cannot be driven externally when in the coprocessor mode. an example of the use of a coprocessor interface is shown in figure 18, in which the c17/e17/p17 are dsps interfaced to the tms70c42, an 8-bit microcontroller. mc mc/pm hi/lo clkout rd tblf ld7 ld6 ld5 ld4 ld3 ld2 ld1 ld0 tms320c17/e17/p17 tms70c42 xtal2 a3 a2 d7 d6 d5 d4 d3 d2 d1 d0 wr rble a1 a0 17 9 8 19 20 21 22 23 24 26 27 7 6 6 32 40 19 20 21 22 23 24 25 26 31 1 3 27 2 figure 18. coprocessor interface
tms320c17, tms320e17, tms320lc17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 100 terminal functions 2 name i/o 3 definition bio clkout d15/ld15-d0/ld0 den /rd dr1, dr0 dx1, dx0 exint fr fsr fsx mc mc/pm pa0/hi/lo pa1/rble pa2/tblf rs sclk v cc v ss we /wr x1 x2/clkin xf i o i/o i/o i o i o i i i i i/o o o i i/o i i o o i o external polling input system clock output, 1/4 crystal/clkin frequency 16-bit parallel data bus/data lines for coprocessor latch data enable for device input data/external read for output latch serial-port receive-channel inputs serial-port transmit-channel outputs external interrupt input internal serial-port framing output external serial-port receive framing input external serial-port transmit framing input microcomputer select (must be same state as mc/pm ) microcomputer/peripheral coprocessor select (must be same state as mc) i/o port address output/latch byte select pin i/o port address output/receive buffer latch empty flag i/o port address output/transmit buffer latch full flag reset for initializing the device serial-port clock + 5 v supply ground write enable for device output data/external write for input latch crystal output for internal oscillator crystal input for internal oscillator or external oscillator system clock input external-flag output pin 2 see eprom programming section. 3 input/output/high-impedance state.
tms320c17, tms320e17, tms320lc17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 101 functional block diagram dr1 dr0 dx1 dx0 rr1/rs1 rr0/rs0 8 16 14 xf 8 8 tr1/ts1 tr0/ts0 8 mux m -law/a-law decoder 8 mux 8 8 16 16 m -law/a-law encoder 16 16 register mux system control 16 16 data latch fr fsx fsr int /exint interrupt latch and multiplexer serial-port timing and framing control mc mc/pm 3 12 32 16 16 16 32 shifter (0,1, 4) 32 acc (32) 32 alu (32) data ram (256 words) address data 32 32 mux 32 16 p(32) t(16) multiplier shifter (016) 16 8 dp 7 mux 8 8 ar1 (16) ar0 (16) arp 16 16 data bus data bus 16 16 16 program bus pa2pa0 12 instruction program rom/eprom (4k words) 3 hi/lo rs bio rd /den wr /we tblf rble stack 4 12 12 12 pc (12) 12 12 lsb mux 16 program bus x2/clkin clkout x1 controller mux mux mux address data latch sclk legend: acc = accumulator pc = program counter arp = auxiliary register pointer p = p register ar0 = auxiliary register 0 t = t register ar1 = auxiliary register 1 tr = transmit register dp = data page pointer rr = receive register d15-d0
v il low-level input voltage v ih high-level input voltage t a operating free-air temperature v cc supply voltage tms320c17, tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 102 electrical specifications this section contains the electrical specifications for all versions of the c17/e17/p17 digital signal processors, including test parameter measurement information. parameters with pp subscripts apply only to the e17/p17 in the eprom programming mode (see note 11). absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v cc , except for the 320lc17 (see note 6) 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range, v pp 0.6 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range 0.3 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous power dissipation 1.5 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature: l suffix 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a suffix 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating condit ionso section of this specification is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliabi lity. note 6: all voltage values are with respect to v ss. recommended operating conditions min nom max unit eprom devices 4.75 5 5.25 v all other devices 4.5 5 5.5 v v pp supply voltage (see note 11) 12.25 12.5 12.75 v v ss supply voltage 0 v all inputs except clkin 2 v clkin 3 v all inputs except mc/mp 0.8 v mc/mp 0.6 v i oh high-level output current, all outputs 300 m a i ol low-level output current (all outputs) 2 ma l suffix 0 70 c a suffix 40 85 c note 11: v pp can be applied only to programming pins designed to accept v pp as an input. during programming the total supply current is i pp + i cc .
ma i cc 3 supply current crystal frequency, f x mhz r l = 825 w , c l = 100 pf (see figure 2) tms320c17, tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 103 electrical characteristics over specified temperature range (unless otherwise noted) parameter test conditions min typ 2 max unit tms320c17 f = 20.5 mhz, v cc = 5.5 v, t a = 0 c to 70 c 50 65 tms320e17/p1 7 f = 25.6 mhz, v cc = 5.5 v, t a = 40 c to 85 c 55 75 2 all typical values are at t a = 70 c and are used for thermal resistance calculations. 3 i cc characteristics are inversely proportional to temperature. for i cc dependance on temperature, frequency, and loading, see figure 3. clock characteristics and timing the c17/e17/p17 can use either its internal oscillator or an external frequency source for a clock. internal clock option the internal oscillator is enabled by connecting a crystal across x1 and x2/clkin (see figure 1). the frequency of clkout is one-fourth the crystal fundamental frequency. the crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mw, and should be specified at a load capacitance of 20 pf. parameter test conditions min nom max unit tms320c17 t a = 0 c to 70 c 6.7 20.5 tms320e17/p1 7 t a = 40 c to 85 c 6.7 20.5 c1, c2 t a = 0 c to 70 c 10 pf external clock option an external frequency source can be used by injecting the frequency directly into x2/clkin with x1 left unconnected. the external frequency injected must conform to the specifications listed in the table below. switching characteristics over recommended operating conditions parameter test conditions min nom max unit t c(c) clkout cycle time 195.12 200 ns t r(c) clkout rise time 10 ? ns t f(c) clkout fall time 8 ? ns t w(cl) pulse duration, clkout low 92 ? ns t w(ch) pulse duration, clkout high 90 ? ns t d(mcc) delay time, clkin to clkout 25 ? 60 ? ns t c(c) is the cycle time of clkout, i.e., 4t c(mc) (4 times clkin cycle time if an external oscillator is used). ? values derived from characterization data and not tested.
r l = 825 w c l = 100 pf, (see figure 2) r l = 825 w , c l = 100 pf (see figure 2) tms320c17, tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 104 timing requirements over recommended operating conditions min nom max unit t c(mc) master clock cycle time 48.78 50 150 ns t r(mc) rise time, master clock input 5 2 10 2 ns t f(mc) fall time, master clock input 5 2 10 2 ns t w(mcp) pulse duration, master clock 0.45t c(mc) 2 0.6t c(mc) 2 ns t w(mcl) pulse duration, master clock low 20 2 ns t w(mch) pulse duration, master clock high 20 2 ns 2 values derived from characterization data and not tested. memory and peripheral interface timing switching characteristics over recommended operating conditions parameter test conditions min typ max unit t d1 delay time, clkout to address bus valid 10 2 50 ns t d4 delay time, clkout to den 1/4t c(c) 5 2 1/4t c(c) +15 ns t d5 delay time, clkout to den 10 2 15 ns t d6 delay time, clkout to we 1/2t c(c) 5 2 1/2t c(c) +15 ns t d7 delay time, clkout to we 10 2 15 ns t d8 delay time, clkout to data bus out valid 1/4t c(c) + 65 ns t d9 time after clkout that data bus starts to be driven 1/4t c(c) 5 2 ns t d10 time after clkout that data bus stops bieng driven 1/4t c(c) +70 2 ns t v data bus out valid after clkout 1/4t c(c) 10 ns t h(a-wmd) address hold time after we , or den (see note 14) 0 2 2 2 ns t su(a-md) address bus setup time prior to den 1/4t c(c) 45 ns 2 values derived from characterization data and not tested. note 14: address bus will be valid upon we , men , or den . timing requirements over recommended operating conditions test conditions min nom max unit t su(d) setup time, data bus valid prior to clkout 50 ns t h(d) hold time, data bus held valid after clkout (see note 16) 0 ns note 16: data may be removed from the data bus upon den preceding clkout .
r l 825 w , c l = 100 pf, (see figure 2) tms320c17, tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 105 reset (rs ) timing switching characteristics over recommended operating conditions parameter test conditions min typ max unit t d11 delay time, den , and we from rs 1/2t c(c) +502 ns t dis(r) data bus disable time after rs 1/4t c(c) +50 2 ns t d12 delay time from rs to high-impedance sclk 200 2 ns t d13 delay time from rs to high-impedance dx1, dx0 200 2 ns 2 values derived form characterization data and not tested. timing requirements over recommended operating conditions min nom max unit t su(r) reset (rs ) setup time prior to clkout (see note 10) 50 ns t w(r) rs pulse duration 5t c(c) ns note 10: rs can occur anytime during a clock cycle. time given is minimum to ensure synchronous operation. interrupt (exint ) timing timing requirements over recommended operating conditions min nom max unit t f(int) fall time, exint 15 ns t w(int) pulse duration, exint t c(c) ns t su(int) setup time, exint before clkout 50 ns io (bio ) timing timing requirements over recommended operating conditions min nom max unit t f(io) fall time, bio 15 ns t w(io) pulse duration, bio t c(c) ns t su(io) setup time, bio before clkout 50 ns switching characteristics over recommended operating conditions parameter test conditions min typ max unit t d(xf) delay time clockout to valid xf r l 825 w , c l = 100 pf, (see figure 2) 5 2 115 ns 2 values derived form characterization data and not tested.
tms320c17, tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 106 serial port timing switching characteristics over recommended operating conditions parameter min nom max unit t d(ch-fr) internal framing (fr) delay from sclk rising edge 70 ns t d(dx1-xl) dx bit 1 valid before sclk falling edge 20 ns t d(dx2-xl) dx bit 2 valid before sclk falling edge 20 ns t h(dx) dx hold time after sclk falling edge t c(sclk) /2 ns timing requirements over recommended operating conditions min nom max unit t c(sclk) serial port clock (sclk) cycle time (see note 17) 390 4770 ns t f(sclk) serial port clock (sclk) fall time 30 2 ns t r(sclk) serial port clock (sclk) rise time 30 2 ns t w(sclkl) serial port clock (sclk) low-pulse duration (see note 17) 185 2500 ns t w(sclkh) serial port clock (sclk) high-pulse duration (see note 17) 185 2500 ns t su(fs) fsx /fsr setup time before sclk falling edge 100 ns t su(dr) dr setup time before sclk falling edge 20 ns t h(dr) dr hold time after sclk falling edge 20 ns 2 values derived from characterization data and not tested. notes: 17. minimum cycle time is 2t c(c) where t c(c) is clkout cycle time. 18. the duty cycle of the serial port clock must be within 45 to 55 percent. coprocessor interface timing switching characteristics over recommended operating conditions parameter min nom max unit t d(r-a) rd low to tblf high 75 ns t d(w-a) wr low to rble high 75 ns t a(rd) rd low to data valid 80 ns t h(rd) data hold time after rd high 25 ns timing requirements over recommended operating conditions min nom max unit t h(hl) hi/lo hold time after wr or rd high 25 ns t su(hl) hi/lo setup time after wr or rd low 40 ns t su(wr) data setup time prior to wr high 30 ns t h(wr) data hold time after wr high 25 ns t w(rdl) rd low-pulse duration 80 ns t w(wrl) wr low-pulse duration 60 ns
tms320c17, tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 107 timing diagrams timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2 volts, unless otherwise noted. clock timing t r(mc) t c(mc) t w(mch) t w(mcp) 2 t f(mc) t w(mcl) t d(mcc) 2 t w(ch) t w(cl) t r(c) t c(c) t f(c) x2/clkin clkout 2 t d(mcc) and t w(mcp) are referenced to an intermediate level of 1.5 v on the clkin waveform. memory read timing t h(awmd) t su(d) t h(d) address bus valid t su(a-md) instruction input valid ckkout a11-a0 d15-d0 t c(c) t d1 t d2 t d3 men
tms320c17, tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 108 in instruction timing clkout men a11-a0 den d15-d0 t su(d) t h(d) t su(a-md) t d5 t d4 12 345 678 legend: 1. in instruction prefetch 5. address bus valid 2. next instruction prefetch 6. instruction input valid 3. address bus valid 7. data input valid 4. peripheral address valid 8. instruction valid out instruction timing clkout men a11-a0 we d15-d0 12 34 5 678 t d6 t d7 t v t d9 t d10 t d8 legend: 1. out instruction prefetch 5. address bus valid 2. next instruction prefetch 6. instruction input valid 3. address bus valid 7. data output valid 4. peripheral address valid 8. instruction valid
tms320c17, tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 109 reset timing t su(r) t su(r) t w(r) t dis(r) t d11 clkout rs den we d15-d0 pa2-pa0 pa = port address valid valid pc = 0 pc = 1 data out sclk dx1, dx0 pa = pc3 + 1 = 1 pc3 = 3 lsb of pc t d13 t d12 pa = pc3 = 0 interrupt timing clkout t su(int) t w(int) t f(int) int bio timing clkout bio t su(io) t w(io) t f(io)
tms320c17, tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 110 xf timing 4 2 1 xf d15-d0 we pa2-pa0 clkout xf valid t d(xf) t v t d9 t d7 3 t d10 t d8 t d6 legend: 1. port address valid 3. port data valid 2. out opcode valid 4. next instruction opcode valid external framing: transmit timing 8 3 2 1 8 3 2 1 t d(dx1-cl) t d(dx2-cl) t h(dx) t su(fs) t w(sclkl) t r(sclk) t w(sclkh) t f(sclk) t su(fs) dx1, dx0 fsx sclk notes: a. data valid on transmit output until sclk rises. b. the most significant bit is shifted first.
tms320c17, tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 111 external framing: receive timing 8 3 2 t su(dr) 1 8 3 2 1 t su(fs) t su(fs) dr1, dr0 fsr sclk t h(dr) note: the most significant bit is shifted first. internal framing: variable-data rate t d(ch-fr) t su(dr) t d(dx2-cl) t d(dx1-cl) dx1, dx0 fr 8 3 2 8 3 2 1 dr1, dr0 sclk t d(ch-fr) 1 t h(dr) note: the most significant bit is shifted first.
tms320c17, tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 112 internal framing: fixed-data rate t d(dx2-cl) t h(dr) t d(dx1-cl) t d(ch-fr) t d(ch-fr) 0 r 8 3 2 8 3 2 1 0 k 1 t su ( dr ) note: the most significant bit is shifted first. coprocessor timing: external write to coprocessor port t h(wr) valid rble data in wr hi/lo t h(wr) t d(w-a ) t su(hl) t h(hl) t h(hl) t su(hl) valid t w(wrl) t w(wrl) only necessary for operation of 8-bit mode constructing 16-bit data t su(wr) t su(wr)
tms320c17, tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 113 coprocessor timing: external read to coprocessor port valid valid t a(rd) tblf data out rd hi/lo t d(r-a) t h(rd) t a(rd) t h(rd) t su(hl) t h(hl) t h(hl) t su(hl) t w(rdl) t w(rdl) only necessary for operation of 8-bit mode constructing 16-bit data
tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 114 eprom programming absolute maximum ratings over specified temperature range (unless otherwise noted) 2 supply voltage range, v pp (see note 6) 0.6 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating condit ionso section of this specification is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliabi lity. note 6: all voltage values are with respect to gnd. recommended operating conditions min nom max unit v pp supply voltage (see note 11) 12.5 12.75 v note 11: v pp can be applied only to programming pins designed to accept v pp as an input. during programming the total supply current is i pp + i cc . electrical characteristics over specified temperature range (unless otherwise noted) parameter test conditions min typ 2 max unit i pp1 v pp supply current v pp = v cc = 5.5 v 100 m a i pp2 v pp supply current (during program pulse) v pp = 12.75 v, v cc = 5.5 v 30 50 ma recommended timing requirements for programming, t a = 25 c, v cc = 6 v, v pp = 12.5 v, (see note 13) min nom max unit t w(ipgm) initial program pulse duration 0.95 1 1.05 ms t w(fpgm) final pulse duration 3.8 63 ms t su(a) address setup time 2 m s t su(e) e setup time 2 m s t su(g) g setup time 2 m s t dis(g) output disable time from g (see note 15) 0 130 3 ns t en(g) output enable time from g 150 3 ns t su(d) data setup time 2 m s t su(vpp) v pp setup time 2 m s t su(vcc) v cc setup time 2 m s t h(a) address hold time 0 m s t h(d) data hold time 2 m s 2 values derived from characterization data and not tested. notes: 13. for all switching characteristics and timing measurements, input pulse levels are 0.4 v to 2.4 v and v pp = 12.5 v 0.25 v during programming. 15. common test conditions apply for t dis(g) except during programming.
tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 115 programming the tms320e17/p17 eprom cell each e17/p17 devices include a 4k 16-bit industry-standard eprom cell for prototyping, early field testing, and low-volume production. in conjunction with this eprom, the tms320c17 with a 4k-word masked rom, then, provides more migration paths for cost-effective production. note: the tms320p17 is a one-time programmable (otp) eprom device. eprom adapter sockets are available that provide pin-to-pin conversions for programming any e17/p17 devices. one adapter socket (part number rtc/pgm320c-06), shown in figure 19, converts a 40-pin dip into an equivalent 28-pin device. another socket (part number rtc/pgm320c-06), not shown, permits 44- to 28-pin conversion. figure 19. eprom adapter socket (40-pin to 28-pin dip conversion) key features of the eprom cell include the normal programming operation as well as verification. the eprom cell also includes a code protection feature that allows code to be protected against copyright violations. the e17/p17 eprom cell is programmed using the same family and device pinout codes as the tms27c64 8k 8-bit eprom. the tms27c64 eprom series are unltraviolet-light erasable, electrically programmable, read-only memories, fabricated using hvcmos technology. they are pin-compatible with existing 28-pin roms and eproms. these eproms operate from a single 5-v supply in the read mode; however, a 12.5-v supply is needed for programming. all programming signals are ttl level. for programming outside the system, existing eprom programmers can be used. locations may be programmed singly, in blocks, or at random. figure 20 shows the wiring conversion to program the e17/p17 using the 28-pin pinout of the tms27c64. table 8 on pin nomenclature provides a description of the tms27c64 pins. the code to be programmed into the device should be in serial mode. the e17/p17 devices use 13 address lines to address 4k-word memory in byte format.
tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 116 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v pp a12 a7 a6 a5 a4 a3 a2 a1 a0 q1 q2 q3 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a1 a0(lsb) vpp rs ept clkin gnd q1(lsb) q2 q3 q4 q5 q6 q7 q8(msb) 40 39 38 37 36 35 34 33 32 30 29 28 27 26 25 24 23 22 21 31 a2 a3 a4 a5 a6 a7 a8 v cc a9 a10 a11 (msb)a12 e g pgm tms320e17/p17 tms27c64 pinout tms27c64 pinout 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc pgm ept a8 a9 a11 g a10 e q8 q7 q6 q5 q4 3.9 k w caution although acceptable by some eprom programmers, the signature mode cannot be used on any tms320e1x device. the signature mode will input a high-level voltage (12.5 v dc ) onto pin a9. since this pin is not designed for high voltage, the cell will be damaged. to prevent an accidental application of voltage, texas instruments has inserted a 3.9 k w resistor between pin a9 of the ti programmer socket and the programmer itself. pin nomenclature (tms320e17/p17) name i/o definition a0-a12 i on-chip eprom programming address lines clkin i clock oscillator input e i eprom chip select ept i eprom test mode select g i eprom read/verify select gnd i ground pgm i eprom write/program select q1-q8 i/o data lines for byte-wide programming of on-chip 8k bytes of eprom rs i reset for initializing the device v cc i 5-v power supply v pp i 12.5-v power supply figure 20. tms320e17/p17 eprom programming conversion to tms27c64 eprom pinout
tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 117 table 8 shows the programming levels required for programming, verifying, reading, and protecting the eprom cell. table 8. tms320e17/p17 programming mode levels signal name tms320e17 pin tms27c64 pin program verify read protect verify eprom protect e 25 20 v il v il v il v il v ih g 24 22 v ih pulse pulse v il v ih pgm 23 27 pulse v ih v ih v ih v ih v pp 3 1 v pp v pp v cc v cc + 1 v pp v cc 30 28 v cc v cc v cc v cc + 1 v cc + 1 v ss 10 14 v ss v ss v ss v ss v ss clkin 8 14 v ss v ss v ss v ss v ss rs 4 14 v ss v ss v ss v ss v ss ept 5 26 v ss v ss v ss v pp v pp q1-q8 11-18 11-13, 15-19 d in q out q out q8=rbit q8=pulse a0-a3 2, 1, 40, 39 10-7 addr addr addr x x a4 38 6 addr addr addr x v ih a5 37 5 addr addr addr x x a6 36 4 addr addr addr v il x a7-a9 35, 34, 29 3, 25, 24 addr addr addr x x a10-a12 28-26 21, 23, 2 addr addr addr x x legend: v ih = ttl high level; v il = ttl low level; addr = byte address bit v pp = 12.5 v 0.25 v; v cc = 5 v 0.25 v; x = don't care pulse = low-going ttl level pulse; d in = byte to be programmed at addr q out = byte stored at addr; rbit = rom protect bit. programming since every memory bit in the cell is a logic 1, the programming operation reprograms certain bits to 0. once programmed, these bits can be erased only by using ultraviolet light. the correct byte is placed on the data bus with v pp set to the 12.5 v level. the pgm pin is then pulsed low to program in the zeroes. erasure before programming, the device must be erased by exposing it to ultraviolet light. the recommended minimum exposure dose (uv-intensity exposure-time) is 15 w ? s/cm 2 . a typical 12-mw/cm 2 , filterless uv lamp will erase the device in 21 minutes. the lamp should be located about 2.5 cm above the chip during erasure. after exposure, all bits are in the high state. verify/read to verify correct programming, the eprom cell can be read using either the verify or read line definitions shown in table 8 assuming the inhibit bit has not been programmed. program inhibit programming may be inhibited by maintaining a high level input on the e pin or pgm pin. read the eprom contents may be read independent of the programming cycle, provided the rbit (rom protect bit) has not been programmed. the read is accomplished by setting e to zero and pulsing g low. the contents of the eprom location selected by the value on the address inputs appear on q8-q1.
tms320e17, tms320p17 digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 118 output disable during the eprom programming process, the eprom data outputs may be disabled, if desired, by establishing the output disable state. this state is selected by setting g and e pins high. while output disable is selected, q8-q1are placed in the high-impedance state. eprom protection to protect the proprietary algorithms existing in the code programmed on-chip, the ability to read or verify code from external accesses can be completely disabled. programming the rbit disables external access of the eprom cell, making it impossible to access the code resident in the eprom cell. the only way to remove this protection is to erase the entire eprom cell, thus removing the proprietary information. the signal requirements for programming this bit are shown in table 8. the cell can be determined as protected by verifying the programming of the rbit shown in the table. standard programming procedure before programming, the device must first be completely erased. the device can then be programmed with the correct code. it is advisable to program unused sections with zeroes as a further security measure. after the programming is complete, the code programmed into the cell should be verified. if the cell passes verification, the next step is to program the rom protect bit (rbit). once the rbit programming is verified, an opaque label should be placed over the window to protect the eprom cell from inadvertent erasure by ambient light. at this point, the programming is complete, and the device is ready to be placed into its destination circuit. program cycle timing a12-a0 q8-q1 v pp v cc e pgm g program verify address stable address n+1 data in stable data out valid t su(a) t h(a) t su(d) t su(vpp) t dis(g) t su(vcc) t su(e) t h(d) t w(ipgm) t w(fpgm) t su(g) t en(g) v ih v il v ih /v oh v il /v ol v pp v cc v cc +1 v cc v ih v il v ih v il v ih v il hi-z
high-level input voltage v ih operating free-air temperature t a v oh high-level output voltage i oz off-state ouput current i i input current c i input capacitance c o output capacitance f = 1 mhz, all other pins 0 v m a m a pf pf tms320lc17 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 119 absolute maximum ratings over specified temperature range (unless otherwise noted) 2 supply voltage range, v cc (see note 6) 0.3 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range 0.3 v to v cc to 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range 0.3 v to v cc to 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous power dissipation 75 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . air temperature range above operating devices: l version 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a version 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range 55 c to +150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the arecommended operating condit ionso section of this specification is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliabi lity. note 6: all voltage values are with respect to v ss . recommended operating conditions min nom max unit v cc supply voltage 3.0 3.3 3.6 v v ss supply voltage 0 v all inputs except clkin 2.0 v clkin 2.5 v v il low-level input voltage all inputs 0.55 v i oh high-level output current (all outputs) 300 m a i ol low-level output current (all outputs) 1.5 ma l version 070 c a version 40 85 c electrical characteristics over specified temperature range (unless otherwise noted) parameter test conditions min typ max unit i oh = max 2.0 v i oh = 20 m a (see note 19) v cc 0.4 ? v v ol low-level output voltage i ol = max 0.5 v v cc = max, v o = v cc 20 v o = v ss 20 v i = v ss to v cc , all inputs except clkin 20 v i = v ss to v cc , clkin 50 data bus 25 ? all others 15 ? data bus 25 ? all others 10 ? all typical values are at v cc = 3.3 v, t a = 25 c. ? values derived from characterization data and not tested. note 19: this voltage specification is included for interface to hc logic. all other timing parameters defined in this data shee t are specified for the test load circuit shown in figure 2.
t a = 40 c to 85 c tms320lc17 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 exint rs mc pa0/hi/lo pa1/rble pa2/tblf fsr fsx fr dx1 d13/ld13 d14/ld14 d15/ld15 d7/ld7 d6/ld6 d5/ld5 d4/ld4 d3/ld3 d2/ld2 ss v ss v d1/ld1 clkout x1 x2/clkin bio nc v ss d8/ld8 d9/ld9 d10/ld10 d11/ld11 d12/ld12 dx0 slck dr1 den /rd we /wr v cc dr0 xf mc/pm d0/ld0 v ss tms320lc17 fn package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pa1/rble pa0/hi/lo mc rs exint clkout x1 x2/clkin bio v ss d8/ld8 d9/ld9 d10/ld10 d11/ld11 d12/ld12 d13/ld13 d14/ld14 d15/ld15 d7/ld7 d6/ld6 pa2/tblf fsr fsx fr dx1 dx0 sclk dr1 den /rd we /wr v cc dr0 xf mc/pm d0/ld0 d1/ld1 d2/ld2 d3/ld3 d4/ld4 d5/ld5 tms320lc17 n package (top view) electrical characteristics over specified ranges (unless otherwise noted) parameter test conditions min typ 2 max unit i cc 3 supply current f = 14.4 mhz, v cc = 3.6 v, t a = 0 c to 70 c 15 20 ma 2 all typical values are at t a = 70 c and are used for thermal resistance calculations. 3 i cc characteristics are inversely proportional to temperature. for i cc dependence on frequency, see figure 3. clock characteristics and timing the tms320lc17 can use either its internal oscillator or an external frequency source for a clock. internal clock option the internal oscillator is enabled by connecting a crystal across x1 and x2/clkin (see figure 1). the frequency of clkout is one-fourth the crystal fundamental frequency. the crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mw, and be specified at a load capacitance of 20 pf. parameter test conditions min nom max unit crystal frequency f x 4.0 14.4 mhz c1, c2 10 pf
r l = 825 w , c l = 100 pf, (see figure 2) r l = 825 w , c l = 100 pf, (see figure 2) tms320lc17 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 121 external clock option an external frequency source can be used by injecting the frequency directly into x2/clkin with x1 left unconnected. the external frequency injected must conform to the specifications listed in the table below. switching characteristics over recommended operating conditions parameter test conditions min nom max unit t c(c) clkout cycle time 277.78 1000 ns t r(c) clkout rise time 10 ? ns t f(c) clkout fall time 8 ? ns t w(cl) pulse duration, clkout low 131 ns t w(ch) pulse duration, clkout high 129 ns t d(mcc) delay time clkin to clkout 25 75 ns t c(c) is the cycle time of clkout, i.e., 4t c(mc) (4 times clkin cycle time if an external oscillator is used). ? values derived from characterization data and not tested timing requirements over recommended operating conditions min nom max unit t c(mc) master clock cycle time 69.5 150 ns t r(mc) rise time, master clock input 5 2 10 2 ns t f(mc) fall time, master clock input 5 2 10 2 ns t w(mcp) pulse duration, master clock 0.4 t c(mc ) 2 0.6 t c(mc ) 2 ns t w(mcl) pulse duration, master clock low at t c(mc) min 30 ns t w(mch) pulse duration, master clock high at t c(mc) min 30 ns 2 values derived from characterization data and not tested. memory and peripheral interface timing switching characteristics over recommended operating conditions parameter test conditions min max unit t d1 delay time clkout to address bus valid 10 2 100 n s t d4 delay time clkout to den 1/4 t c(c) 5 2 1/4 t c(c) +25 ns t d5 delay time clkout to den 10 2 30 ns t d6 delay time clkout to we 1/2 t c(c) 5 2 1/2 t c(c) +25 ns t d7 delay time clkout to we 10 2 30 ns t d8 delay time clkout to data bus out valid 1/4 t c(c) +130 ns t d9 time after clkout that data bus starts to be driven 1/4 t c(c) 5 2 ns t d10 time after clkout that data bus stops being driven 1/4 t c(c) +90 ns t v data bus out valid after clkout 1/4 t c(c) 10 ns t h(a-wmd) address hold time after we , men , or den (see note 14) 0 2 ns t su(a-md) address bus setup time or den 0 ns 2 values derived from characterization data and not tested. note 14: address bus will be valid upon we , men , or den .
r l = 825 w , c l = 100 pf, (see figure 2) r l = 825 w , c l = 100 pf, (see figure 2) tms320lc17 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 122 timing requirements over recommended operating conditions test conditions min nom max unit t su(d) setup time data bus valid prior to clkout 80 ns t h(d) hold time data bus held valid after clkout (see note 9) 0 ns note 9: data may be removed from the data bus upon men or den preceding clkout . reset (rs ) timing switching characteristics over recommended operating conditions parameter test conditions min nom max unit t d11 delay time den , we , and men from rs 1/2t c(c) +75 ns t dis(r) data bus disable time after rs 1/4t c(c) +75 ns t d12 delay time from rs to high-impedance sclk 200 2 ns t d13 delay time from rs to high-impedance dx1, dx0 200 2 ns 2 these values were derived from characterization data and not tested. timing requirements over recommended operating conditions min nom max unit t su(r) reset (rs ) setup time prior to clkout (see note 10) 85 ns t w(r) rs pulse duration 5t c(c) ns note 10: rs can occur anytime during a clock cycle. time given is minimum to ensure synchronous operation. interrupt (exint ) timing timing requirements over recommended operating conditions min nom max unit t f(int) fall time exint 15 ns t w(int) pulse duration exint t c(c) ns t su(int) setup time exint before clkout 85 ns i/o (bio ) timing timing requirements over recommended operating conditions min nom max unit t f(io) fall time bio 15 ns t w(io) pulse duration bio t c(c) ns t su(io) setup time bio before clkout 85 ns
r l = 825 w , c l = 100 pf, (see figure 2) tms320lc17 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 123 i/o (bio ) timing switching characteristics over recommended operating conditions parameter test conditions min nom max unit t d(xf) delay time clkout to valid xf 5 2 115 ns 2 values derived from characterization data and not tested. serial port timing switching characteristics over recommended operating conditions min nom max unit t d(ch-fr) internal framing (fr) delay from sclk rising edge 120 ns t d(dx1-cl) dx bit 1 valid before sclk falling edge 20 ns t d(dx2-cl) dx bit 2 valid before sclk falling edge 20 ns t h(dx) dx hold time after sclk falling edge t c(sclk) /2 ns timing requirements over recommended operating conditions min nom max unit t c(sclk) serial port clock (sclk) cycle time 3 555 8000 ns t f(sclk) serial port clock (sclk) fall time 30 2 ns t r(sclk) serial port clock (sclk) rise time 30 2 ns t w(sclk) serial port clock (sclk) low, pulse duration 250 4400 ns t w(sclkh) serial port clock (sclk) high, pulse duration 250 4400 ns t su(fs) fsx /fsr setup time before sclk falling edge 130 ns t su(dr) dr setup time before sclk falling edge 20 ns t h(dr) dr hold time after sclk falling edge 20 ns 2 values derived from characterization data and not tested. 3 minimum cycle time is 2t c(c) where t c(c) is clkout cycle time. the duty cycle of the serial port clock must be within 45 to 55%.
tms320lc17 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 124 coprocessor interface timing switching characteristics over recommended operating conditions min nom max unit t d(r-a) rd low to tblf high 150 ns t d(w-a) wr low to rblf high 150 ns t a(rd) rd low to data valid 150 ns t h(rd) data hold time after rd high 25 timing requirements over recommended operating conditions min nom max unit t h(hl) hi/rd hold time after wr or rd high 25 ns t su(hl) hi/rd setup time prior to wr or rd low 40 ns t su(wr) data setup time prior to wr high 50 ns t h(wr) data hold time after wr high 35 ns t w(rdl) pulse duration, rd low 150 ns t w(wrl) pulse duration, wr low 150 ns
tms320lc17 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 125 clock timing t r(mc) t c(mc) t w(mch) t w(mcp) 2 t f(mc) t w(mcl) t d(mcc) 2 t w(ch) t w(cl) t r(c) t c(c) t f(c) x2/clkin clkout 2 t d(mcc) and t w(mcp) are referenced to an intermediate level of 1.5 v on the clkin waveform. in instruction timing clkout men pa2-pa0 den d15-d0 t su(d) t h(d) t su(a-md) t d5 t d4 12 345 678 legend: 1. in instruction prefetch 5. address bus valid 2. next instruction prefetch 6. instruction valid 3. address bus valid 7. data input valid 4. peripheral address valid 8. instruction valid
tms320lc17 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 126 out instruction timing clkout men pa2-pa0 we d15-d0 12 34 5 678 t d6 t d7 t d8 t v t d9 t d10 legend: 1. out instruction prefetch 5. address bus valid 2. next instruction prefetch 6. instruction valid 3. address bus valid 7. data output valid 4. peripheral address valid 8. instruction valid reset timing t su(r) t su(r) t w(r) t dis(r) t d11 clkout rs den we d15-d0 pa2-pa0 pa = port address valid valid pc = 0 pc = 1 data out sclk dx1, dx0 pa = pc3 + 1 = 1 pc3 = 3 lsb of pc t d13 t d12 pa = pc3 = 0
tms320lc17 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 127 interrupt timing clkout t su(int) t w(int) t f(int) int bio timing clkout bio t su(io) t w(io) t f(io) xf timing 4 2 1 xf d15-d0 we pa2-pa0 clkout xf valid t d(xf) t v t d9 t d7 3 t d10 t d8 t d6 legend: 1. port address valid 3. port data valid 2. out opcode valid 4. next instruction opcode valid
tms320lc17 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 128 external framing: transmit timing 8 3 2 1 8 3 2 1 t d(dx1-cl) t d(dx2-cl) t h(dx) t su(fs) t w(sclkl) t r(sclk) t w(sclkh) t f(sclk) t su(fs) dx1, dx0 fsx sclk notes: a. data valid on transmit output until sclk rises. b. the most significant bit is shifted first. external framing: receive timing 8 3 2 t su(dr) 1 8 3 2 1 t su(fs) t su(fs) dr1, dr0 fsr sclk t h(dr) note b: the most significant bit is shifted first.
tms320lc17 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 129 internal framing: variable-data rate t d(ch-fr) t su(dr) t d(dx2-cl) t d(dx1-cl) dx1, dx0 fr 8 3 2 8 3 2 1 dr1, dr0 sclk t d(ch-fr) 1 t h(dx) t h(dr) note: the most significant bit is shifted first. internal framing: fixed-data rate t d(dx2-cl) t h(dr) t d(dx1-cl) t d(ch-fr) t d(ch-fr) dx1, dx0 fr 8 3 2 8 3 2 1 dr1, dr0 sclk 1 t h(dx) t su(dr) note: the most significant bit is shifted first.
tms320lc17 digital signal processor sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 130 coprocessor timing: external write to coprocessor port t h(wr) valid data in wr hi/lo t h(wr) t su(hl) t h(hl) t h(hl) t su(hl) valid t w(wrl) t w(wrl) t su(wr) t su(wr) rble t d(w-a) only necessary for operation of 8-bit mode constructing 16-bit data coprocessor timing: external read to coprocessor port valid valid t a(rd) tblf data out rd hi/lo t d(r-a) t h(rd) t a(rd) t h(rd) t su(hl) t h(hl) t h(hl) t su(hl) t w(rdl) t w(rdl) only necessary for operation of 8-bit mode constructing 16-bit data
device tms320c1x digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 131 thermal resistance characteristics commercial devices device/package thermal resistance junction to case r q jc ( c/w) pdip (n) cdip (jd) plcc (fn) clcc (fz) qfp (pg) tms320c10 26 17 tms320c10-14 26 17 tms320c10-25 26 17 tms320c14 11 tms320e14 8 tms320p14 11 tms320c15 26 17 TMS320C15-25 26 17 tms320e15 8 8 tms320e15-25 8 8 tms320lc15 26 17 tms320p15 13 13 tms320c16 25 tms320c17 26 17 tms320e17 8 8 tms320lc17 26 17 tms320p17 13 13
device tms320c1x digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 132 thermal resistance characteristics commercial devices device/package thermal resistance junction to ambient r q ja ( c/w) pdip (n) cdip (jd) plcc (fn) clcc (fz) qfp (pg) tms320c10 84 60 tms320c10-14 84 60 tms320c10-25 84 60 tms320c14 46 tms320e14 49 tms320p14 46 tms320c15 84 60 TMS320C15-25 84 60 tms320e15 40 64 tms320e15-25 40 64 tms320lc15 84 60 tms320p15 40 55 tms320c16 120 tms320c17 84 60 tms320e17 40 64 tms320lc17 84 60 tms320p17 40 55
tms320c1x digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 133 mechanical data 40-pin plastic dual-in-line package either or both index marks 53,1 (2.090) max 5,08 (0.200) max 2,92 (0.115) min 1,52 (0.060) nom 2,54 (0.100) t.p. pin spacing (see note a) 0,84 (0.033) min 0,457 0,076 (0.018 0.003) seating plane 40 21 21 1 0,51 (0.020) min 2,41 (0.095) 1,40 (0.055) 15,24 0,25 (0.600 0.010) c l c l 105 90 all dimensions are in millimeters and parenthetically in inches 0,28 0,08 (0.011 0.003) note a: each pin centerline is located within 0,254 (0.010) of its true longitudinal position. 40-pin windowed ceramic dual-in-line package 123456789 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 c l c l 51,31 (2.020) max index dot seating plane 4,70 (0.185) max 105 90 2,54 (0.100) t.p. pin spacing (see note a) 0,508 (0.020) min 1,27 0,508 (0.050 0.020) 0,457 0,076 (0.018 0.003) 1,27 0,254 (0.050 0.010) 3,81 0,762 (0.150 0.030) 15,24 0,25 (0.600 0.010) all dimensions are in millimeters and parenthetically in inches 15,0 (0.590) nom 0,25(0.010) nom note a: each pin centerline is located within 0,254 (0.010) of its true longitudinal position.
tms320c1x digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 134 44-lead plastic chip carrier (fn suffix) all linear dimensions are in millimeters and parenthetically in inches 16,66 (0.656) 16,51 (0.650) 17,65 (0.695) 17,40 (0.685) 16,66 (0.656) 16,51 (0.650) 17,65 (0.695) 17,40 (0.685) index dot 1,14 (0.045) 45 typ 4,57 (0.180) 4,19 (0.165) 3,05 (0.120) 2,29 (0.090) 0,51 (0.020) min 0,533 (0.021) 0,330 (0.013) 16,00 (0.630) 14,99 (0.590) 1,27 (0.050) typ
tms320c1x digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 135 64-pin quad flat pack (pg suffix) (tms320c16) 0,1 (0.004) min 0 -10 0,35 (0.0014) typ 1,0 (0.039) typ 64 20 32 52 51 33 19 1 3,10 (0.122) max 20,0 (0.787) nom 14,0 (0.552) nom 18,0 (0.709) 17,2 (0.677) 24,0 (0.945) 23,2 (0.913) 0,20 (0.008) 0,10 (0.004) 1,0 (0.040) 0,6 (0.024) c l c l all linear dimensions are in millimeters and parenthetically in inches
lead detail 0,64 (0.025) min 1,52 (0.060) min seating plane 0,25 (0.010) r max in 3 places ?? ?? 24,33 (0.956) 24,13 (0.950) (see note a) 24,33 (0.956) 24,13 (0.950) (see note a) 25,27 (0.995) 25,02 (0.985) 0,81 (0.032) 0,66 (0.026) 23,62 (0.930) 23,11 (0.910) (at seating plane) 4,50 (0.177) 4,24 (0.167) 2,79 (0.110) 2,41 (0.095) 1,35 (0.053) 1,19 (0.047) 45 0,94 (0.037) 0,69 (0.027) r 1,27 (0.050) t.p. (see note b) 25,27 (0.995) 25,02 (0.985) 0,51 (0.020) 0,36 (0.014) 1,22 (0.048) 1,07 (0.042) 45 notes: a. centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by this deminsion. b. location of each pin is within 0,27 (0.005) of true position with respect to center pin on each side. tms320c1x digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 136 mechanical data 68-lead plastic chip carrier package (fn suffix) all linear dimensions are in millimeters and parenthetically in inches
0,51 (0.020) 0,36 (0.014) 0,81 (0.032) 0,66 (0.026) 0,64 (0.025) r max typ, 3 places 3,55 (0.140) 3,05 (0.120) 4,57 (0.180) 3,94 (0.155) b a a b c (at seating plane) 1.02 (0.040) 45 1,27 (0.05) typ (see note b) 1.016 (0.040) min (see note a) 3,05 (0.120) 2,29 (0.090) seating plane (see note c) optional eprom window tms320c1x digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 137 mechanical data 68-lead ceramic chip carrier package (fz suffix) a b c min max min max min max m0-087aa 28 12,32 (0.485) 12,57 (0.495) 10,92 (0.430) 11,56 (0.455) 10,41 (0.410) 10.92 (0.430) m0-087ab 44 17,40 (0.685) 17,65 (0.695) 16,00 (0.630) 16,64 (0.655) 15,49 0.610) 16,00 (0.630) m0-087ad 68 25,02 (0.985) 25,27 (0.995) 23,62 (0.930) 24,26 (0.955) 23.11 (0.910) 23,62 (0.930) notes: a. centerline of center pin each side is within 0,10 (0.004) of package centerline as determined by dimension b. b. location of each pin is within 0,27 (0.005) of true position with respect to center pin on each side. c. the lead contact points are planar within 0,15 (0.006) all linear dimensions are in millimeters and parenthetically in inches
tms320c1x digital signal processors sprs009c january 1987 revised july 1991 post office box 1443 ? houston, texas 77001 138 index accumulator/alu 5 . . . . . . . . . . . . . . . . . . . . . . architecture (tms320c1x family) 5, 6 . . . . . . tms320c14 32 . . . . . . . . . . . . . . . . . . . . . . . tms320c17 96 . . . . . . . . . . . . . . . . . . . . . . . functional block diagram tms320c10 13 . . . . . . . . . . . . . . . . . . . . . . . tms320c14 32 . . . . . . . . . . . . . . . . . . . . . . . tms320c15 53 . . . . . . . . . . . . . . . . . . . . . . . tms320c16 82 . . . . . . . . . . . . . . . . . . . . . . . tms320c17 95 . . . . . . . . . . . . . . . . . . . . . . . codec interface tms320c17 3, 6, 96 98 . . . . . . . . . . . . . . companding hardware tms320c17 3, 96, 97 . . . . . . . . . . . . . . . . . . control register tms320c17 97 . . . . . . . . . . . . . . . . . . . . . . . coprocessor interface 98 . . . . . . . . . . . . . . . . . data memory 2, 3, 5, 33 . . . . . . . . . . . . . . . . . . description tms320c10 2, 3, 11 . . . . . . . . . . . . . . . . . . . tms320c14 2, 3, 28, 29 . . . . . . . . . . . . . . . tms320c15 2, 3, 52 . . . . . . . . . . . . . . . . . . . tms320lc15 2, 3, 70 . . . . . . . . . . . . . . . . . . tms320c16 2, 3, 79 . . . . . . . . . . . . . . . . . . . tms320c17 2, 3, 95 . . . . . . . . . . . . . . . . . . . tms320lc17 2, 3, 120 . . . . . . . . . . . . . . . . . electrical specifications tms320c10 14 . . . . . . . . . . . . . . . . . . . . . . . tms320c14 35 . . . . . . . . . . . . . . . . . . . . . . . tms320c15 55 . . . . . . . . . . . . . . . . . . . . . . . tms320lc15 69 . . . . . . . . . . . . . . . . . . . . . . tms320c16 83 . . . . . . . . . . . . . . . . . . . . . . . tms320c17 102 . . . . . . . . . . . . . . . . . . . . . . tms320lc17 120 . . . . . . . . . . . . . . . . . . . . . eprom programming tms320e14/p14 47 . . . . . . . . . . . . . . . . . . . tms320e15/p15 65 . . . . . . . . . . . . . . . . . . . tms320e17/p17 114 . . . . . . . . . . . . . . . . . . framing pulses tms320c17/lc17/e17/p17 97 . . . . . . . . . instruction set 7 . . . . . . . . . . . . . . . . . . . . . . . . . interrupts 6, 33 . . . . . . . . . . . . . . . . . . . . . . . . . . interfacing to sram/eprom/peripherals tms320c16 90 . . . . . . . . . . . . . . . . . . . . . . . i/o channels 2, 3, 6, 28, 79, 95 . . . . . . . . . . . . key features (tms320c1x) 1 . . . . . . . . . . . . . . tms320c10 11 . . . . . . . . . . . . . . . . . . . . . . . tms320c14 28 . . . . . . . . . . . . . . . . . . . . . . . tms320c15 52 . . . . . . . . . . . . . . . . . . . . . . . tms320c16 79 . . . . . . . . . . . . . . . . . . . . . . . tms320c17 95 . . . . . . . . . . . . . . . . . . . . . . . mechanical data 133 137 . . . . . . . . . . . . . . . memory (tms320c1x) 2, 3, 5 . . . . . . . . . . . . . tms320c10 11 . . . . . . . . . . . . . . . . . . . . . . . tms320c14 28 . . . . . . . . . . . . . . . . . . . . . . . tms320c15 52 . . . . . . . . . . . . . . . . . . . . . . . tms320c16 79 . . . . . . . . . . . . . . . . . . . . . . . tms320c17 95 . . . . . . . . . . . . . . . . . . . . . . . microcomputer/microprocessor mode 5, 33 . . microcomputer/coprocessor 7, 98 . . . . . . . . . . multiplier 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package types (tms320c1x) 4 . . . . . . . . . . . . pinout/nomenclature tms320c10 4, 11 . . . . . . . . . . . . . . . . . . . . . tms320c14 4, 28 . . . . . . . . . . . . . . . . . . . . . tms320c15 4, 52 . . . . . . . . . . . . . . . . . . . . . tms320lc15 4, 70 . . . . . . . . . . . . . . . . . . . . tms320c16 4, 79 . . . . . . . . . . . . . . . . . . . . . tms320c17 4, 95 . . . . . . . . . . . . . . . . . . . . . tms320lc17 4, 120 . . . . . . . . . . . . . . . . . . . serial port tms320c17/e17 6, 96 . . . . . . . . . . . . . . . . . shifters 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . subroutines 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . terminal functions tms320c10 12 . . . . . . . . . . . . . . . . . . . . . . . tms320c14 30 . . . . . . . . . . . . . . . . . . . . . . . tms320c15 54 . . . . . . . . . . . . . . . . . . . . . . . tms320c16 80 . . . . . . . . . . . . . . . . . . . . . . . tms320c17 100 . . . . . . . . . . . . . . . . . . . . . . thermal data 27, 131, 132 . . . . . . . . . . . . . . . . . timing diagrams tms320c10 23 26 . . . . . . . . . . . . . . . . . . . tms320c14 41 46, 51 . . . . . . . . . . . . . . . tms320c15 60 63, 68 . . . . . . . . . . . . . . . tms320lc15 75 78 . . . . . . . . . . . . . . . . . . tms320c16 86 91 . . . . . . . . . . . . . . . . . . . tms320c17 107 113, 118 . . . . . . . . . . . . tms320lc17 125 130 . . . . . . . . . . . . . . .
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 5962-8763308qa active cdip sb jd 40 1 tbd call ti level-nc-nc-nc 5962-8763308ya active jlcc fj 44 1 tbd call ti level-nc-nc-nc smj320c15-25fjm active jlcc fj 44 1 tbd call ti level-nc-nc-nc smj320c15-25jdm active cdip sb jd 40 1 tbd call ti level-nc-nc-nc tms320c10fna obsolete 44 tbd call ti call ti tms320c10fnl obsolete plcc fn 44 tbd cu snpb level-3-220c-168hr tms320c10fnl25 nrnd plcc fn 44 26 tbd cu snpb level-3-220c-168hr tms320c10na obsolete pdip n 40 tbd cu snpb level-nc-nc-nc tms320c10nl nrnd pdip n 40 9 tbd cu snpb level-nc-nc-nc tms320c10nl-25 nrnd pdip n 40 9 tbd cu snpb level-nc-nc-nc tms320c10nl25 obsolete 0 tbd call ti call ti tms320c14fnl nrnd plcc fn 68 tbd call ti call ti tms320c15fna obsolete plcc fn 44 tbd call ti call ti tms320c15fnl obsolete plcc fn 44 tbd call ti call ti tms320c15fnl25 obsolete plcc fn 44 tbd call ti call ti tms320c15na obsolete pdip n 40 tbd call ti call ti tms320c15nl obsolete pdip n 40 tbd call ti call ti tms320c15nl-25 obsolete pdip n 40 tbd call ti call ti tms320c15nl25 obsolete plcc nl 40 tbd call ti call ti tms320c15pel obsolete qfp pe 44 tbd call ti call ti tms320c16pgl obsolete qfp pg 64 tbd call ti call ti tms320c17fnl obsolete plcc fn 44 tbd call ti call ti tms320c17nl obsolete pdip n 40 tbd call ti call ti tms320lc15fnl obsolete plcc fn 44 tbd call ti call ti tms320lc15nl obsolete pdip n 40 tbd call ti call ti tms320p14fnl obsolete plcc fn 68 tbd cu snpb level-3-220c-168hr tms320p15fnl obsolete plcc fn 44 tbd call ti call ti tms320p15fnl25 obsolete plcc fn 44 tbd call ti call ti tms320p15na obsolete pdip n 40 tbd call ti call ti tms320p15nl obsolete pdip n 40 tbd call ti call ti tms320p15nl25 obsolete pdip n 40 tbd call ti call ti tms320p17fna obsolete plcc fn 44 tbd call ti call ti tms320p17fnl obsolete plcc fn 44 tbd call ti call ti tms320p17fnlr obsolete plcc fn 44 tbd call ti call ti tms320p17nl obsolete pdip n 40 tbd call ti call ti tms320ss16nl obsolete pdip n 40 tbd call ti call ti (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. package option addendum www.ti.com 5-dec-2005 addendum-page 1
(2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 5-dec-2005 addendum-page 2
mechanical data mcdi005 ? january 1998 post office box 655303 ? dallas, texas 75265 jd (r-cdip-t**) ceramic side-braze dual-in-line package 24 pins shown 0.590 (14,99) 0.620 (15,75) typ 0.590 (15,00) 52 0.012 (0,30) 0.008 (0,20) 48 2.435 40 2.050 0.020 (0,51) min 0.125 (3,18) min (61,85) (52,07) (67,31) 2.650 4040087/b 04/95 seating plane a 13 12 0.045 (1,14) 0.065 (1,65) 24 1 0.075 (1,91) max (4 places) 28 24 pins ** 0.021 (0,53) 0.015 (0,38) 1.250 (31,75) dim a max 0.175 (4,45) 0.140 (3,56) (36,83) 1.450 0.100 (2,54) 0 ?15 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package is hermetically sealed with a metal lid. d. the terminals are gold-plated.

mechanical data mpdi008 october 1994 post office box 655303 ? dallas, texas 75265 n (r-pdip-t**) plastic dual-in-line package 24 pin shown 12 seating plane 0.560 (14,22) 0.520 (13,21) 13 0.610 (15,49) 0.590 (14,99) 52 48 40 0.125 (3,18) min 2.390 (60,71) (62,23) (53,09) (51,82) 2.040 2.090 2.450 2.650 (67,31) (65,79) 2.590 0.010 (0,25) nom 4040053 / b 04/95 a 0.060 (1,52) typ 1 24 32 28 24 1.230 (31,24) (32,26) (36,83) (35,81) 1.410 1.450 1.270 pins ** dim 0.015 (0,38) 0.021 (0,53) a min a max 1.650 (41,91) (40,89) 1.610 0.020 (0,51) min 0.200 (5,08) max 0.100 (2,54) m 0.010 (0,25) 0 15 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-011 d. falls within jedec ms-015 (32 pin only)
mechanical data mplc004a october 1994 1 post office box 655303 ? dallas, texas 75265 fn (s-pqcc-j**) plastic j-leaded chip carrier 4040005 / b 03/95 20 pin shown 0.026 (0,66) 0.032 (0,81) d2 / e2 0.020 (0,51) min 0.180 (4,57) max 0.120 (3,05) 0.090 (2,29) d2 / e2 0.013 (0,33) 0.021 (0,53) seating plane max d2 / e2 0.219 (5,56) 0.169 (4,29) 0.319 (8,10) 0.469 (11,91) 0.569 (14,45) 0.369 (9,37) max 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.008 (0,20) nom 1.158 (29,41) 0.958 (24,33) 0.756 (19,20) 0.191 (4,85) 0.141 (3,58) min 0.441 (11,20) 0.541 (13,74) 0.291 (7,39) 0.341 (8,66) 18 19 14 13 d d1 1 3 9 e1 e 4 8 min max min pins ** 20 28 44 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 52 68 84 1.185 (30,10) 0.985 (25,02) 0.785 (19,94) d/e 0.395 (10,03) 0.495 (12,57) 1.195 (30,35) 0.995 (25,27) 0.695 (17,65) 0.795 (20,19) no. of d1 / e1 0.350 (8,89) 0.450 (11,43) 1.150 (29,21) 0.950 (24,13) 0.650 (16,51) 0.750 (19,05) 0.004 (0,10) m 0.007 (0,18) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-018
mechanical data mqfp008 july 1998 1 post office box 655303 ? dallas, texas 75265 pg (r-pqfp-g64) plastic quad flatpack 4040101 / b 03/95 0,15 nom 18,00 14,20 13,80 17,20 32 33 20 19 12,00 typ 0,25 1,10 0,70 0,10 min gage plane 51 1 18,00 typ 52 64 23,20 24,00 19,80 20,20 3,10 max 2,70 typ 0,25 0,45 0 10 seating plane 0,10 1,00 m 0,20 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. contact field sales office to determine if a tighter coplanarity requirement is available for this package.
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